Chirania; Manoj

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chirania; Manoj.The latest application filed is for "programmable logic block having reduced output delay during ram write processes when programmed to function in ram mode".

Company Profile

0.18.0

Chirania; Manoj - Palo Alto CA
Chirania; Manoj - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode Grant 7,804,719 - Chirania , et al. September 28, 2	2010-09-28
Method of reducing power of a circuit Grant 7,653,891 - Anderson , et al. January 26, 2	2010-01-26
Method for simulation of negative bias and temperature instability Grant 7,600,204 - Chirania , et al. October 6, 2	2009-10-06
Estimating LUT power usage Grant 7,552,410 - Chirania June 23, 2	2009-06-23
Process monitor vehicle Grant 7,518,394 - Chirania , et al. April 14, 2	2009-04-14
Lookup table with relatively balanced delays Grant 7,471,104 - Chirania December 30, 2	2008-12-30
Integrated circuit including a multiplexer circuit Grant 7,423,452 - Chirania September 9, 2	2008-09-09
Circuits and methods of implementing flip-flops in dual-output lookup tables Grant 7,385,416 - Chirania , et al. June 10, 2	2008-06-10
Interconnect driver circuits for dynamic logic Grant 7,382,157 - Young , et al. June 3, 2	2008-06-03
Lookup table circuits programmable to implement flip-flops Grant 7,378,869 - Chirania , et al. May 27, 2	2008-05-27
Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure Grant 7,375,552 - Young , et al. May 20, 2	2008-05-20
Programmable logic block with carry chains providing lookahead functions of different lengths Grant 7,268,587 - Pham , et al. September 11, 2	2007-09-11
Programmable lookup table with dual input and output terminals in RAM mode Grant 7,265,576 - Kondapalli , et al. September 4, 2	2007-09-04
Programmable lookup table with dual input and output terminals in shift register mode Grant 7,215,138 - Kondapalli , et al. May 8, 2	2007-05-08
Programmable logic block having improved performance when functioning in shift register mode Grant 7,202,697 - Kondapalli , et al. April 10, 2	2007-04-10
Method of measuring performance of a semiconductor device and circuit for the same Grant 7,119,570 - Chirania , et al. October 10, 2	2006-10-10
High performance programmable logic devices utilizing dynamic circuitry Grant 7,116,131 - Chirania , et al. October 3, 2	2006-10-03
Lookup table circuit optionally configurable as two or more smaller lookup tables with independent inputs Grant 6,998,872 - Chirania , et al. February 14, 2	2006-02-14

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