Chinthakindi; Anil Kumar

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chinthakindi; Anil Kumar.The latest application filed is for "fuse structure including monocrystalline semiconductor material layer and gap".

Company Profile

0.8.9

Chinthakindi; Anil Kumar - Wappingers Falls NY
Chinthakindi; Anil Kumar - Poughkeepsie NY
Chinthakindi; Anil Kumar - Haymarket VA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material Grant 7,915,134 - Chinthakindi , et al. March 29, 2	2011-03-29
Post last wiring level inductor using patterned plate process Grant 7,763,954 - Chinthakindi , et al. July 27, 2	2010-07-27
Post last wiring level inductor using patterned plate process Grant 7,741,698 - Chinthakindi , et al. June 22, 2	2010-06-22
Post last wiring level inductor using patterned plate process Grant 7,732,294 - Chinthakindi , et al. June 8, 2	2010-06-08
Post last wiring level inductor using patterned plate process Grant 7,732,295 - Chinthakindi , et al. June 8, 2	2010-06-08
Fuse structure including monocrystalline semiconductor material layer and gap Grant 7,713,792 - Chinthakindi , et al. May 11, 2	2010-05-11
Post last wiring level inductor using patterned plate process Grant 7,573,117 - Chinthakindi , et al. August 11, 2	2009-08-11
Fuse Structure Including Monocrystalline Semiconductor Material Layer And Gap App 20090096059 - Chinthakindi; Anil Kumar ; et al.	2009-04-16
Method of Integration of a MIM Capacitor with a Lower Plate of Metal Gate Material Formed on an STI Region or a Silicide Region Formed in or on the Surface of a Doped Well with a High K Dielectric Material App 20090004809 - Chinthakindi; Anil Kumar ; et al.	2009-01-01
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080293210 - Chinthakindi; Anil Kumar ; et al.	2008-11-27
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080290458 - Chinthakindi; Anil Kumar ; et al.	2008-11-27
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080293233 - Chinthakindi; Anil Kumar ; et al.	2008-11-27
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080277759 - Chinthakindi; Anil Kumar ; et al.	2008-11-13
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080272458 - Chinthakindi; Anil Kumar ; et al.	2008-11-06
Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric Grant 7,361,950 - Chinthakindi , et al. April 22, 2	2008-04-22
Integration Of A Mim Capacitor Over A Metal Gate Or Silicide With High-k Dielectric Materials App 20070057343 - Chinthakindi; Anil Kumar ; et al.	2007-03-15
Post Last Wiring Level Inductor Using Patterned Plate Process App 20070026659 - Chinthakindi; Anil Kumar ; et al.	2007-02-01

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