Ching, Jr.; Mariano Layson
Patent Applications and Registrations
Patent applications and USPTO patent grants for Ching, Jr.; Mariano Layson.The latest application filed is for "lead reduction for improved creepage distance".
- Ching, Jr.; Mariano Layson - Tianjin CN
| Patent | Date |
|---|---|
| Lead frame with selective patterned plating Grant 10,847,449 - Song , et al. November 24, 2 | 2020-11-24 |
| Hybrid lead frame for semiconductor die package with improved creepage distance Grant 10,734,311 - Ching, Jr. , et al. | 2020-08-04 |
| Lead reduction for improved creepage distance Grant 10,734,327 - Ching, Jr. , et al. | 2020-08-04 |
| Hybrid Lead Frame For Semiconductor Die Package With Improved Creepage Distance App 20200203262 - CHING, JR.; Mariano Layson ; et al. | 2020-06-25 |
| Lead Frame With Selective Patterned Plating App 20200203258 - Song; Meijiang ; et al. | 2020-06-25 |
| Lead Reduction For Improved Creepage Distance App 20200203289 - CHING, JR.; Mariano Layson ; et al. | 2020-06-25 |
| Packaged integrated circuit having stacked die and method for therefor Grant 10,446,476 - Higgins, III , et al. Oc | 2019-10-15 |
| Packaged Integrated Circuit Having Stacked Die And Method For Therefor App 20190088576 - HIGGINS, III; LEO M. ; et al. | 2019-03-21 |
| Pressure-sensing integrated circuit device with diaphragm Grant 10,151,658 - Ching, Jr. , et al. Dec | 2018-12-11 |
| Pressure-sensing Integrated Circuit Device With Diaphragm App 20170292884 - CHING, JR.; MARIANO LAYSON ; et al. | 2017-10-12 |
| Lead frame and substrate semiconductor package Grant 9,190,353 - Ching, Jr. , et al. November 17, 2 | 2015-11-17 |
| Lead Frame And Substrate Semiconductor Package App 20140252581 - CHING, JR.; MARIANO LAYSON ; et al. | 2014-09-11 |
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