Chin; Pin-Shyne

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chin; Pin-Shyne.The latest application filed is for "reducing device mismatch by adjusting titanium formation".

Company Profile

0.7.5

Chin; Pin-Shyne - Hsin-Chu TW
Chin; Pin-Shyne - Shinchu TW
Chin; Pin-Shyne - Hsinchu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Reducing Device Mismatch by Adjusting Titanium Formation App 20110084391 - Cheng; Shyh-Wei ; et al.	2011-04-14
Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device Grant 7,244,641 - Chin July 17, 2	2007-07-17
Resist protect oxide structure of sub-micron salicide process Grant 7,183,150 - Hsieh , et al. February 27, 2	2007-02-27
Low leakage one transistor static random access memory Grant 7,064,371 - Chin , et al. June 20, 2	2006-06-20
Novel resist protect oxide structure of sub-micron salicide process App 20050037623 - Hsieh, Ming-Chang ; et al.	2005-02-17
Method to modify 0.25 .mu.m 1T-RAM by extra resist protect oxide (RPO) blocking Grant 6,852,589 - Huang , et al. February 8, 2	2005-02-08
Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device Grant 6,849,485 - Chin February 1, 2	2005-02-01
Low leakage one transistor static random access memory App 20050009271 - Chin, Pin-Shyne ; et al.	2005-01-13
Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device App 20050003596 - Chin, Pin-Shyne	2005-01-06
Resist protect oxide structure of sub-micron salicide process Grant 6,815,274 - Hsieh , et al. November 9, 2	2004-11-09
Low leakage one transistor static random access memory Grant 6,790,724 - Chin , et al. September 14, 2	2004-09-14
Method to modify 0.25 mum 1T-RAM by extra resist protect oxide (RPO) blocking App 20030148576 - Huang, Ching-Kwun ; et al.	2003-08-07

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