Chin; Bryan W.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Chin; Bryan W..The latest application filed is for "collapsed address translation with multiple page sizes".
- Chin; Bryan W. - San Diego CA
| Patent | Date |
|---|---|
| Distributed interrupt scheme in a multi-processor system Grant 10,394,730 - Chin , et al. A | 2019-08-27 |
| Collapsed address translation with multiple page sizes Grant 10,042,778 - Mukherjee , et al. August 7, 2 | 2018-08-07 |
| Distributed timer subsystem Grant 9,928,193 - Worrell , et al. March 27, 2 | 2018-03-27 |
| Collapsed Address Translation With Multiple Page Sizes App 20170206171 - Mukherjee; Shubhendu S. ; et al. | 2017-07-20 |
| Apparatus and method for distributed instruction trace in a processor system Grant 9,703,669 - Lampert , et al. July 11, 2 | 2017-07-11 |
| Collapsed address translation with multiple page sizes Grant 9,645,941 - Mukherjee , et al. May 9, 2 | 2017-05-09 |
| Merged TLB structure for multiple sequential address translations Grant 9,639,476 - Chin , et al. May 2, 2 | 2017-05-02 |
| Distributed timer subsystem across multiple devices Grant 9,568,944 - Worrell , et al. February 14, 2 | 2017-02-14 |
| Debug interface for multiple CPU cores Grant 9,404,970 - Lin , et al. August 2, 2 | 2016-08-02 |
| Inter-chip interconnect protocol for a multi-chip system Grant 9,372,800 - Akkawi , et al. June 21, 2 | 2016-06-21 |
| Apparatus And Method For Distributed Instruction Trace In A Processor System App 20160140014 - Lampert; Gerald ; et al. | 2016-05-19 |
| Distributed Timer Subsystem App 20160140066 - Worrell; Frank ; et al. | 2016-05-19 |
| Distributed Interrupt Scheme In A Multi-processor System App 20160140064 - CHIN; Bryan W. ; et al. | 2016-05-19 |
| Debug Interface For Multiple Cpu Cores App 20160139201 - Lin; Teng Chiang ; et al. | 2016-05-19 |
| Distributed Timer Subsystem Across Multiple Devices App 20160139625 - Worrell; Frank ; et al. | 2016-05-19 |
| Maintenance of cache and tags in a translation lookaside buffer Grant 9,268,694 - Snyder, II , et al. February 23, 2 | 2016-02-23 |
| Translation bypass in multi-stage address translation Grant 9,208,103 - Kessler , et al. December 8, 2 | 2015-12-08 |
| Inter-chip Interconnect Protocol For A Multi-chip System App 20150254183 - Akkawi; Isam ; et al. | 2015-09-10 |
| Translation Bypass In Multi-Stage Address Translation App 20150089150 - Kessler; Richard E. ; et al. | 2015-03-26 |
| Merged TLB Structure For Multiple Sequential Address Translations App 20150089116 - Chin; Bryan W. ; et al. | 2015-03-26 |
| Collapsed Address Translation With Multiple Page Sizes App 20150089184 - Mukherjee; Shubhendu S. ; et al. | 2015-03-26 |
| Maintenance Of Cache And Tags In A Translation Lookaside Buffer App 20150089147 - Snyder, II; Wilson P. ; et al. | 2015-03-26 |
| High speed variable bandwidth ring-based system Grant 8,989,220 - Scrobohaci , et al. March 24, 2 | 2015-03-24 |
| High Speed Variable Bandwidth Ring-Based System App 20130315236 - Scrobohaci; Paul G. ; et al. | 2013-11-28 |
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