Childs; Lawrence F.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Childs; Lawrence F..The latest application filed is for "memory device and sense circuitry therefor".
- Childs; Lawrence F. - Austin TX
| Patent | Date |
|---|---|
| Memory Device And Sense Circuitry Therefor App 20110128807 - Sharma; Ashish ; et al. | 2011-06-02 |
| Dual port memory device Grant 7,940,599 - Lu , et al. May 10, 2 | 2011-05-10 |
| Memory having self-timed bit line boost circuit and method therefor Grant 7,800,959 - Childs , et al. September 21, 2 | 2010-09-21 |
| Dual Port Memory Device App 20100232202 - Lu; Olga R. ; et al. | 2010-09-16 |
| Memory having a dummy bitline for timing control Grant 7,746,716 - Jetton , et al. June 29, 2 | 2010-06-29 |
| Memory Having Self-timed Bit Line Boost Circuit And Method Therefor App 20100074032 - Childs; Lawrence F. ; et al. | 2010-03-25 |
| Memory Having A Dummy Bitline For Timing Control App 20080205176 - Jetton; Mark W. ; et al. | 2008-08-28 |
| SRAM having variable power supply and method therefor Grant 7,292,485 - Lu , et al. November 6, 2 | 2007-11-06 |
| Layout for noise reduction on a reference voltage Grant 5,670,815 - Childs , et al. September 23, 1 | 1997-09-23 |
| Power-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memory Grant 5,477,176 - Chang , et al. December 19, 1 | 1995-12-19 |
| Write control for a memory using a delay locked loop Grant 5,440,514 - Flannagan , et al. August 8, 1 | 1995-08-08 |
| Latching ECL to CMOS input buffer circuit Grant 5,426,381 - Flannagan , et al. June 20, 1 | 1995-06-20 |
| Memory having looped global data lines for propagation delay matching Grant 5,400,274 - Jones , et al. March 21, 1 | 1995-03-21 |
| Pipelined memory having synchronous and asynchronous operating modes Grant 5,384,737 - Childs , et al. January 24, 1 | 1995-01-24 |
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