Child; Craig

Patent Applications and Registrations

Patent applications and USPTO patent grants for Child; Craig.The latest application filed is for "multiple patterning with mandrel cuts defined by block masks".

Company Profile

3.10.9

Child; Craig - Gansevoort NY
Child; Craig - Wilton NY
Child; Craig - Hopewell Junction NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multiple patterning with mandrel cuts defined by block masks Grant 11,417,525 - O'Toole , et al. August 16, 2	2022-08-16
Multiple Patterning With Mandrel Cuts Defined By Block Masks App 20200111668 - O'Toole; Martin ; et al.	2020-04-09
Interconnect formation with chamferless via, and related interconnect Grant 10,566,231 - O'Toole , et al. Feb	2020-02-18
Interconnect Formation With Chamferless Via, And Related Interconnect App 20190333805 - O'Toole; Martin J. ; et al.	2019-10-31
Integrated circuits including magnetic tunnel junctions for magnetoresistive random-access memory and methods for fabricating the same Grant 9,691,971 - Nam , et al. June 27, 2	2017-06-27
Unique Bi-layer Etch Stop To Protect Conductive Structures During A Metal Hard Mask Removal Process And Methods Of Using Same App 20160372413 - Mahalingam; Anbu Selvam ; et al.	2016-12-22
Methods of producing integrated circuits with an air gap Grant 9,431,294 - He , et al. August 30, 2	2016-08-30
Integrated Circuits Including Magnetic Tunnel Junctions For Magnetoresistive Random-access Memory And Methods For Fabricating The Same App 20160190207 - Nam; Seowoo ; et al.	2016-06-30
Integrated Circuits With An Air Gap And Methods Of Producing The Same App 20160118292 - He; Ming ; et al.	2016-04-28
Methods for fabricating integrated circuits using improved masks Grant 9,165,770 - He , et al. October 20, 2	2015-10-20
Methods For Fabricating Integrated Circuits Using Improved Masks App 20150087149 - He; Ming ; et al.	2015-03-26
Method to reduce depth delta between dense and wide features in dual damascene structures Grant 8,822,342 - Srivastava , et al. September 2, 2	2014-09-02
Method of manufacturing an interconnect structure for a semiconductor device Grant 8,513,109 - Child August 20, 2	2013-08-20
Method To Reduce Depth Delta Between Dense And Wide Features In Dual Damascene Structures App 20120168957 - SRIVASTAVA; Ravi Prakash ; et al.	2012-07-05
Method Of Manufacturing An Interconnect Structure For A Semiconductor Device App 20110171822 - CHILD; Craig	2011-07-14
Interconnect structure for a semiconductor device Grant 7,932,613 - Child April 26, 2	2011-04-26
Interconnect Structure For A Semiconductor Device And Related Method Of Manufacture App 20100244267 - CHILD; Craig	2010-09-30

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