loadpatents
name:-0.023205995559692
name:-0.01116681098938
name:-0.010213136672974
Chien; Wu-Yi Henry Patent Filings

Chien; Wu-Yi Henry

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chien; Wu-Yi Henry.The latest application filed is for "vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays".

Company Profile
10.12.25
  • Chien; Wu-Yi Henry - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Vertical Thin-film Transistor And Application As Bit-line Connector For 3-dimensional Memory Arrays
App 20220293623 - Yan; Tianhong ;   et al.
2022-09-15
Methods for forming multilayer horizontal NOR-type thin-film memory strings
Grant 11,404,431 - Herner , et al. August 2, 2
2022-08-02
Vertical thing-film transistor and application as bit-line connector for 3-dimensional memory arrays
Grant 11,398,492 - Yan , et al. July 26, 2
2022-07-26
3-dimensional Nor Memory Array Architecture And Methods For Fabrication Thereof
App 20220199643 - Harari; Eli ;   et al.
2022-06-23
Thin-film Storage Transistor With Ferroelectric Storage Layer
App 20220173251 - Samachisa; George ;   et al.
2022-06-02
Methods For Forming Multi-layer Vertical Nor-type Memory String Arrays
App 20220165751 - Herner; Scott Brad ;   et al.
2022-05-26
3-dimensional NOR memory array architecture and methods for fabrication thereof
Grant 11,309,331 - Harari , et al. April 19, 2
2022-04-19
Methods for forming multi-layer vertical NOR-type memory string arrays
Grant 11,282,855 - Herner , et al. March 22, 2
2022-03-22
Silicon Oxide Nitride Tunnel Dielectric For A Storage Transistor In A 3-dimensional Nor Memory String Array
App 20220028871 - Herner; Scott Brad ;   et al.
2022-01-27
Process for a 3-dimensional array of horizontal NOR-type memory strings
Grant 11,217,600 - Purayath , et al. January 4, 2
2022-01-04
Charge-trapping Layer With Optimized Number Of Charge-trapping Sites For Fast Program And Erase Of A Memory Cell In A 3-dimensional Nor Memory String Array
App 20210320182 - Chien; Wu-Yi Henry ;   et al.
2021-10-14
3-dimensional Nor Memory Array With Very Fine Pitch: Device And Method
App 20210313348 - Harari; Eli ;   et al.
2021-10-07
Epitaxial Monocrystalline Channel for Storage Transistors in 3-Dimensional Memory Structures and Methods for Formation Thereof
App 20210280605 - Hu; Chenming ;   et al.
2021-09-09
Cool Electron Erasing In Thin-film Storage Transistors
App 20210226071 - Salahuddin; Sayeef ;   et al.
2021-07-22
3-dimensional nor memory array with very fine pitch: device and method
Grant 11,069,711 - Harari , et al. July 20, 2
2021-07-20
Device structure for a 3-dimensional NOR memory array and methods for improved erase operations applied thereto
Grant 11,069,696 - Harari , et al. July 20, 2
2021-07-20
Vertical Thin-film Transistor And Application As Bit-line Connector For 3-dimensional Memory Arrays
App 20210210506 - Yan; Tianhong ;   et al.
2021-07-08
Epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof
Grant 11,049,873 - Hu , et al. June 29, 2
2021-06-29
Process For Preparing A Channel Region Of A Thin-film Transistor In A 3-dimensional Thin-film Transistor Array
App 20210193660 - Purayath; Vinod ;   et al.
2021-06-24
Process For A 3-dimensional Array Of Horizontal Nor-type Memory Strings
App 20210013224 - Purayath; Vinod ;   et al.
2021-01-14
3-dimensional Nor Memory Array Architecture And Methods For Fabrication Thereof
App 20200403002 - Harari; Eli ;   et al.
2020-12-24
Processes For Forming 3-dimensional Horizontal Nor Memory Arrays
App 20200365609 - Harari; Eli ;   et al.
2020-11-19
3-dimensional NOR memory array architecture and methods for fabrication thereof
Grant 10,818,692 - Harari , et al. October 27, 2
2020-10-27
3-dimensional Nor Memory Array With Very Fine Pitch: Device And Method
App 20200303414 - Harari; Eli ;   et al.
2020-09-24
3-dimensional Nor Memory Array Architecture And Methods For Fabrication Thereof
App 20200258903 - A1
2020-08-13
Device With Embedded High-bandwidth, High-capacity Memory Using Wafer Bonding
App 20200258897 - A1
2020-08-13
Fabrication method for a 3-dimensional NOR memory array
Grant 10,741,581 - Harari , et al. A
2020-08-11
3-dimensional NOR memory array with very fine pitch: device and method
Grant 10,741,584 - Harari , et al. A
2020-08-11
3-dimensional Nor Memory Array With Very Fine Pitch: Device And Method
App 20200203378 - Harari; Eli ;   et al.
2020-06-25
Methods For Forming Multi-layer Vertical Nor-type Memory String Arrays
App 20200185411 - Herner; Scott Brad ;   et al.
2020-06-11
Methods For Forming Multilayer Horizontal Nor-type Thin-film Memory Strings
App 20200176468 - Herner; Scott Brad ;   et al.
2020-06-04
3-dimensional NOR memory array with very fine pitch: device and method
Grant 10,622,377 - Harari , et al.
2020-04-14
Staircase Structures for Electrically Connecting Multiple Horizontal Conductive Layers of a 3-Dimensional Memory Device
App 20200098779 - Cernea; Raul Adrian ;   et al.
2020-03-26
Epitaxial Monocrystalline Channel for Storage Transistors in 3-Dimensional Memory Structures and Methods for Formation Thereof
App 20200098789 - Hu; Chenming ;   et al.
2020-03-26
Device Structure for a 3-Dimensional NOR Memory Array and Methods for Improved Erase Operations Applied Thereto
App 20200051990 - Harari; Eli ;   et al.
2020-02-13
Fabrication Method for a 3-Dimensional NOR Memory Array
App 20200020718 - Harari; Eli ;   et al.
2020-01-16
3-Dimensional NOR Memory Array with Very Fine Pitch: Device and Method
App 20190206890 - Harari; Eli ;   et al.
2019-07-04

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