Chidambarrao; Dureseti

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chidambarrao; Dureseti.The latest application filed is for "exploratory data interface".

Company Profile

10.200.200

Chidambarrao; Dureseti - Weston CT
Chidambarrao; Dureseti - Westin CT
Chidambarrao; Dureseti - Hopewell Junction NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stacked via rivets in chip hotspots Grant 11,308,257 - Chidambarrao , et al. April 19, 2	2022-04-19
Multi-mode design and operation for transistor mismatch immunity Grant 11,303,285 - Strom , et al. April 12, 2	2022-04-12
Exploratory Data Interface App 20210240921 - Fry; Jonathan ; et al.	2021-08-05
Circuit Layout Similarity Metric For Semiconductor Testsite Coverage App 20200364316 - Topaloglu; Rasit Onur ; et al.	2020-11-19
Circuit layout similarity metric for semiconductor testsite coverage Grant 10,839,133 - Topaloglu , et al. November 17, 2	2020-11-17
Optimizing integrated circuit designs based on interactions between multiple integration design rules Grant 10,628,544 - Chidambarrao , et al.	2020-04-21
Deep trench floorplan distribution design methodology for semiconductor manufacturing Grant 10,614,190 - Chidambarrao , et al.	2020-04-07
Optimizing integrated circuit designs based on interactions between multiple integration design rules Grant 10,592,627 - Chidambarrao , et al.	2020-03-17
Deep Trench Floorplan Distribution Design Methodology For Semiconductor Manufacturing App 20200004910 - Chidambarrao; Dureseti ; et al.	2020-01-02
Optimizing Integrated Circuit Designs Based On Interactions Between Multiple Integration Design Rules App 20190095551 - Chidambarrao; Dureseti ; et al.	2019-03-28
Optimizing Integrated Circuit Designs Based On Interactions Between Multiple Integration Design Rules App 20190095550 - Chidambarrao; Dureseti ; et al.	2019-03-28
Integrated circuit (IC) design analysis and feature extraction Grant 9,754,071 - Nanjundappa , et al. September 5, 2	2017-09-05
Integrated Circuit (ic) Design Analysis And Feature Extraction App 20170242952 - Nanjundappa; Haraprasad ; et al.	2017-08-24
Modeling transistor performance considering non-uniform local layout effects Grant 9,646,124 - Chidambarrao , et al. May 9, 2	2017-05-09
Optical proximity correction (OPC) accounting for critical dimension (CD) variation from inter-level effects Grant 9,536,039 - Banerjee , et al. January 3, 2	2017-01-03
Modeling Transistor Performance Considering Non-uniform Local Layout Effects App 20160378888 - Chidambarrao; Dureseti ; et al.	2016-12-29
Optical Proximity Correction (opc) Accounting For Critical Dimension (cd) Variation From Inter-level Effects App 20160217249 - Banerjee; Shayak ; et al.	2016-07-28
High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture Grant 9,401,424 - Chen , et al. July 26, 2	2016-07-26
Optical proximity correction (OPC) accounting for critical dimension (CD) variation from inter-level effects Grant 9,342,648 - Banerjee , et al. May 17, 2	2016-05-17
Correcting for stress induced pattern shifts in semiconductor manufacturing Grant 9,311,443 - Chidambarrao , et al. April 12, 2	2016-04-12
Stress-generating structure for semiconductor-on-insulator devices Grant 9,305,999 - Zhu , et al. April 5, 2	2016-04-05
Correcting For Stress Induced Pattern Shifts In Semiconductor Manufacturing App 20150363536 - Chidambarrao; Dureseti ; et al.	2015-12-17
Optical Proximity Correction (opc) Accounting For Critical Dimension (cd) Variation From Inter-level Effects App 20150356230 - Banerjee; Shayak ; et al.	2015-12-10
Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor Grant 9,082,877 - Liang , et al. July 14, 2	2015-07-14
Circuit Technique To Electrically Characterize Block Mask Shifts App 20150179536 - Acar; Emrah ; et al.	2015-06-25
Structure and method for mobility enhanced MOSFETs with unalloyed silicide Grant 9,059,316 - Liu , et al. June 16, 2	2015-06-16
Silicon device on SI:C-OI and SGOI and method of manufacture Grant 9,040,373 - Chidambarrao , et al. May 26, 2	2015-05-26
High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture Grant 9,023,698 - Chen , et al. May 5, 2	2015-05-05
Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers Grant 8,993,395 - Chidambarrao , et al. March 31, 2	2015-03-31
Methods and system for analysis and management of parametric yield Grant 8,997,028 - Culp , et al. March 31, 2	2015-03-31
Circuit technique to electrically characterize block mask shifts Grant 8,969,104 - Acar , et al. March 3, 2	2015-03-03
High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture Grant 8,901,566 - Chen , et al. December 2, 2	2014-12-02
Complementary Metal Oxide Semiconductor (cmos) Device Having Gate Structures Connected By A Metal Gate Conductor App 20140349451 - Liang; Yue ; et al.	2014-11-27
High Performance Stress-enhanced Mosfets Using Si:c And Sige Epitaxial Source/drain And Method Of Manufacture App 20140322873 - Chen; Huajie ; et al.	2014-10-30
Silicon nanotube MOSFET Grant 8,871,576 - Tekleab , et al. October 28, 2	2014-10-28
Silicon nanotube MOSFET Grant 8,866,266 - Tekleab , et al. October 21, 2	2014-10-21
MOS having a sic/sige alloy stack Grant 8,835,234 - Chidambarrao , et al. September 16, 2	2014-09-16
Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor Grant 8,803,243 - Liang , et al. August 12, 2	2014-08-12
Silicon Device On Si:c-oi And Sgoi And Method Of Manufacture App 20140103366 - CHIDAMBARRAO; Dureseti ; et al.	2014-04-17
Silicon Nanotube Mosfet App 20140061583 - Tekleab; Daniel ; et al.	2014-03-06
Structure and method for mobility enhanced MOSFETS with unalloyed silicide Grant 8,642,434 - Liu , et al. February 4, 2	2014-02-04
Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same Grant 8,629,022 - Chidambarrao , et al. January 14, 2	2014-01-14
Stress-generating structure for semiconductor-on-insulator devices Grant 8,629,501 - Zhu , et al. January 14, 2	2014-01-14
Circuit Technique To Electrically Characterize Block Mask Shifts App 20130320340 - Acar; Emrah ; et al.	2013-12-05
Minimizing Leakage Current And Junction Capacitance In Cmos Transistors By Utilizing Dielectric Spacers App 20130288440 - Chidambarrao; Dureseti ; et al.	2013-10-31
Mos Having A Sic/sige Alloy Stack App 20130273699 - Chidambarrao; Dureseti ; et al.	2013-10-17
Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers Grant 8,541,814 - Chidambarrao , et al. September 24, 2	2013-09-24
Methods And System For Analysis And Management Of Parametric Yield App 20130238263 - Culp; James A. ; et al.	2013-09-12
Multiple orientation nanowires with gate stack sensors Grant 8,492,802 - Chidambarrao , et al. July 23, 2	2013-07-23
IC having viabar interconnection and related method Grant 8,492,268 - Chidambarrao , et al. July 23, 2	2013-07-23
Stress-generating Structure For Semiconductor-on-insulator Devices App 20130168804 - Zhu; Huilong ; et al.	2013-07-04
Cmos Having A Sic/sige Alloy Stack App 20130168695 - Chidambarrao; Dureseti ; et al.	2013-07-04
Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor App 20130168776 - Liang; Yue ; et al.	2013-07-04
CMOS having a SiC/SiGe alloy stack Grant 8,476,706 - Chidambarrao , et al. July 2, 2	2013-07-02
Selective partial gate stack for improved device isolation Grant 8,466,496 - Yu , et al. June 18, 2	2013-06-18
Circuit analysis using transverse buckets Grant 8,453,100 - Chidambarrao , et al. May 28, 2	2013-05-28
Selective Partial Gate Stack For Improved Device Isolation App 20130126976 - Yu; Xiaojun ; et al.	2013-05-23
Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same Grant 8,445,974 - Chidambarrao , et al. May 21, 2	2013-05-21
Methods and system for analysis and management of parametric yield Grant 8,429,576 - Culp , et al. April 23, 2	2013-04-23
Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance Grant 8,418,087 - Banerjee , et al. April 9, 2	2013-04-09
Field effect transistor having multiple conduction states Grant 8,405,165 - Chidambarrao , et al. March 26, 2	2013-03-26
Multiple Orientation Nanowires with Gate Stack Sensors Grant 8,367,492 - Chidambarrao , et al. February 5, 2	2013-02-05
Multiple orientation nanowires with gate stack stressors Grant 8,368,125 - Chidambarrao , et al. February 5, 2	2013-02-05
Multiple Orientation Nanowires With Gate Stack Sensors App 20130015507 - Chidambarrao; Dureseti ; et al.	2013-01-17
Communication App 20120322215 - CHIDAMBARRAO; Dureseti ; et al.	2012-12-20
Semiconductor nanowires having mobility-optimized orientations Grant 8,299,565 - Sekaric , et al. October 30, 2	2012-10-30
Efuse containing sige stack Grant 8,299,570 - Kim , et al. October 30, 2	2012-10-30
IC having viabar interconnection and related method Grant 8,299,622 - Chidambarrao , et al. October 30, 2	2012-10-30
Compact model methodology for PC landing pad lithographic rounding impact on device performance Grant 8,302,040 - Chidambarrao , et al. October 30, 2	2012-10-30
Methodology for improving device performance prediction from effects of active area corner rounding Grant 8,296,691 - Chidambarrao , et al. October 23, 2	2012-10-23
Minimizing Leakage Current And Junction Capacitance In Cmos Transistors By Utilizing Dielectric Spacers App 20120261672 - Chidambarrao; Dureseti ; et al.	2012-10-18
Formation of improved SOI substrates using bulk semiconductor wafers Grant 8,268,698 - Henson , et al. September 18, 2	2012-09-18
Methods And System For Analysis And Management Of Parametric Yield App 20120227019 - Culp; James A. ; et al.	2012-09-06
Silicon Nanotube MOSFET App 20120217468 - Tekleab; Daniel ; et al.	2012-08-30
Nanowire devices for enhancing mobility through stress engineering Grant 8,237,150 - Chidambarrao , et al. August 7, 2	2012-08-07
Methods and system for analysis and management of parametric yield Grant 8,239,790 - Culp , et al. August 7, 2	2012-08-07
High Performance Stress-enhanced Mosfets Using Si:c And Sige Epitaxial Source/drain And Method Of Manufacture App 20120196412 - CHEN; Huajie ; et al.	2012-08-02
Silicon device on Si:C-OI and SGOI and method of manufacture Grant 8,232,153 - Chidambarrao , et al. July 31, 2	2012-07-31
Film wrapped NFET nanowire Grant 8,232,165 - Chidambarrao , et al. July 31, 2	2012-07-31
Structure and method for mobility enhanced MOSFETs with unalloyed silicide Grant 8,217,423 - Liu , et al. July 10, 2	2012-07-10
Asymmetric Fet Including Sloped Threshold Voltage Adjusting Material Layer And Method Of Fabricating Same App 20120171831 - Chidambarrao; Dureseti ; et al.	2012-07-05
Ic Having Viabar Interconnection And Related Method App 20120164758 - Chidambarrao; Dureseti ; et al.	2012-06-28
Structure And Method For Mobility Enhanced Mosfets With Unalloyed Silicide App 20120146092 - Liu; Yaocheng ; et al.	2012-06-14
Structure And Method For Mobility Enhanced Mosfets With Unalloyed Silicide App 20120149159 - Liu; Yaocheng ; et al.	2012-06-14
Analyzing Multiple Induced Systematic And Statistical Layout Dependent Effects On Circuit Performance App 20120144356 - Banerjee; Shayak ; et al.	2012-06-07
Stress-generating Structure For Semiconductor-on-insulator Devices App 20120139081 - Zhu; Huilong ; et al.	2012-06-07
Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance Grant 8,176,444 - Banerjee , et al. May 8, 2	2012-05-08
High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture Grant 8,168,489 - Chen , et al. May 1, 2	2012-05-01
Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain Grant 8,168,971 - Chidambarrao , et al. May 1, 2	2012-05-01
Circuit Analysis Using Transverse Buckets App 20120054711 - Chidambarrao; Dureseti ; et al.	2012-03-01
Silicon device on Si:C SOI and SiGe and method of manufacture Grant 8,119,472 - Chidambarrao , et al. February 21, 2	2012-02-21
Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same Grant 8,115,254 - Zhu , et al. February 14, 2	2012-02-14
Methods And System For Analysis And Management Of Parametric Yield App 20110307846 - Culp; James A. ; et al.	2011-12-15
Efuse Containing Sige Stack App 20110272779 - Kim; Deok-Kee ; et al.	2011-11-10
Film Wrapped Nfet Nanowire App 20110275198 - Chidambarrao; Dureseti ; et al.	2011-11-10
Hybrid orientation scheme for standard orthogonal circuits Grant 8,053,844 - Chidambarrao November 8, 2	2011-11-08
Methods and system for analysis and management of parametric yield Grant 8,042,070 - Culp , et al. October 18, 2	2011-10-18
System and methodology for determining layout-dependent effects in ULSI simulation Grant 8,037,433 - Chidambarrao , et al. October 11, 2	2011-10-11
Compact Model Methodology For Pc Landing Pad Lithographic Rounding Impact On Device Performance App 20110225562 - Chidambarrao; Dureseti ; et al.	2011-09-15
Embedded stressed nitride liners for CMOS performance improvement Grant 8,013,397 - Chidambarrao , et al. September 6, 2	2011-09-06
Structurally stabilized semiconductor nanowire Grant 8,013,324 - Chidambarrao , et al. September 6, 2	2011-09-06
eFuse containing SiGe stack Grant 8,004,059 - Kim , et al. August 23, 2	2011-08-23
Asymmetric semiconductor devices and method of fabricating Grant 7,999,332 - Yuan , et al. August 16, 2	2011-08-16
Semiconductor nanowire with built-in stress Grant 7,989,233 - Sekaric , et al. August 2, 2	2011-08-02
Semiconductor Nanowires Having Mobility-optimized Orientations App 20110175063 - Sekaric; Lidija ; et al.	2011-07-21
Compact model methodology for PC landing pad lithographic rounding impact on device performance Grant 7,979,815 - Chidambarrao , et al. July 12, 2	2011-07-12
Asymmetric Fet Including Sloped Threshold Voltage Adjusting Material Layer And Method Of Fabricating Same App 20110163385 - Chidambarrao; Dureseti ; et al.	2011-07-07
Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers App 20110147885 - Henson; William K. ; et al.	2011-06-23
Strained silicon on relaxed sige film with uniform misfit dislocation density Grant 7,964,865 - Chidambarrao , et al. June 21, 2	2011-06-21
Structure and method for mosfet with reduced extension resistance Grant 7,960,237 - Chidambarrao , et al. June 14, 2	2011-06-14
Gate electrode stress control for finFET performance enhancement description Grant 7,960,801 - Chidambarrao June 14, 2	2011-06-14
eFuse with partial SiGe layer and design structure therefor Grant 7,960,809 - Kothandaraman , et al. June 14, 2	2011-06-14
Electrical fuse having a fully silicided fuselink and enhanced flux divergence Grant 7,943,493 - Chidambarrao , et al. May 17, 2	2011-05-17
Semiconductor nanowires having mobility-optimized orientations Grant 7,943,530 - Sekaric , et al. May 17, 2	2011-05-17
Intersect area based ground rule for semiconductor design Grant 7,941,780 - Avanessian , et al. May 10, 2	2011-05-10
Semiconductor Nanowire With Built-in Stress App 20110104860 - Sekaric; Lidija ; et al.	2011-05-05
Formation of improved SOI substrates using bulk semiconductor wafers Grant 7,932,158 - Henson , et al. April 26, 2	2011-04-26
Device having dual etch stop liner and reformed silicide layer and related methods Grant 7,928,571 - Chidambarrao , et al. April 19, 2	2011-04-19
Semiconductor nanowire with built-in stress Grant 7,902,541 - Sekaric , et al. March 8, 2	2011-03-08
Film Wrapped NFET Nanowire App 20110049473 - Chidambarrao; Dureseti ; et al.	2011-03-03
Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer Grant 7,888,197 - Chidambarrao , et al. February 15, 2	2011-02-15
Nanostructure For Changing Electric Mobility App 20110012177 - Chidambarrao; Dureseti ; et al.	2011-01-20
Multiple Orientation Nanowires With Gate Stack Stressors App 20110012176 - CHIDAMBARRAO; Dureseti ; et al.	2011-01-20
Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification Grant 7,863,197 - Chen , et al. January 4, 2	2011-01-04
Electrical Fuse Having A Fully Silicided Fuselink And Enhanced Flux Divergence App 20100330783 - Chidambarrao; Dureseti ; et al.	2010-12-30
Method and structure for improving device performance variation in dual stress liner technology Grant 7,843,024 - Chidambarrao , et al. November 30, 2	2010-11-30
Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon Grant 7,838,932 - Chakravarti , et al. November 23, 2	2010-11-23
Electrical fuse having a fully silicided fuselink and enhanced flux divergence Grant 7,838,963 - Chidambarrao , et al. November 23, 2	2010-11-23
Asymmetric Semiconductor Devices and Method of Fabricating App 20100289085 - Yuan; Jun ; et al.	2010-11-18
CA resistance variability prediction methodology Grant 7,831,941 - Chidambarrao , et al. November 9, 2	2010-11-09
Analyzing Multiple Induced Systematic and Statistical Layout Dependent Effects On Circuit Performance App 20100269079 - Banerjee; Shayak ; et al.	2010-10-21
Automated optimization of device structure during circuit design stage Grant 7,818,692 - Chidambarrao , et al. October 19, 2	2010-10-19
Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof Grant 7,812,397 - Cheng , et al. October 12, 2	2010-10-12
Semiconductor Nanowire With Built-in Stress App 20100252801 - Sekaric; Lidija ; et al.	2010-10-07
Structurally Stabilized Semiconductor Nanowire App 20100252815 - Chidambarrao; Dureseti ; et al.	2010-10-07
Semiconductor Nanowires Having Mobility-optimized Orientations App 20100252814 - Sekaric; Lidija ; et al.	2010-10-07
Nanowire Devices For Enhancing Mobility Through Stress Engineering App 20100252800 - Chidambarrao; Dureseti ; et al.	2010-10-07
High performance stress-enhance MOSFET and method of manufacture Grant 7,791,144 - Chidambarrao , et al. September 7, 2	2010-09-07
Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer Grant 7,781,800 - Chen , et al. August 24, 2	2010-08-24
Semiconductor device structure having low and high performance devices of same conductive type on same substrate Grant 7,776,695 - Arnold , et al. August 17, 2	2010-08-17
Multiple conduction state devices having differently stressed liners Grant 7,768,041 - Chidambarrao , et al. August 3, 2	2010-08-03
Efuse With Partial Sige Layer And Design Structure Therefor App 20100181643 - Kothandaraman; Chandrasekharan ; et al.	2010-07-22
Semiconductor device stress modeling methodology Grant 7,761,278 - Chidambarrao , et al. July 20, 2	2010-07-20
Transistor with dielectric stressor elements Grant 7,759,739 - Chidambarrao , et al. July 20, 2	2010-07-20
Structure and method to improve channel mobility by gate electrode stress modification Grant 7,750,410 - Belyansky , et al. July 6, 2	2010-07-06
MOSFET performance improvement using deformation in SOI structure Grant 7,745,277 - Chidambarrao , et al. June 29, 2	2010-06-29
Creating increased mobility in a bipolar device Grant 7,741,186 - Chidambarrao , et al. June 22, 2	2010-06-22
Reduction of boron diffusivity in pFETs Grant 7,737,014 - Buehrer , et al. June 15, 2	2010-06-15
Method for fabricating a semiconductor structure Grant 7,732,288 - Zhu , et al. June 8, 2	2010-06-08
Device having enhanced stress state and related methods Grant 7,732,270 - Chidambarrao , et al. June 8, 2	2010-06-08
Gate Electrode Stress Control For Finfet Performance Enhancement Description App 20100127327 - Chidambarrao; Dureseti	2010-05-27
Semiconductor structure for low parasitic gate capacitance Grant 7,709,910 - Henson , et al. May 4, 2	2010-05-04
High performance strained silicon FinFETs device and method for forming same Grant 7,705,345 - Bedell , et al. April 27, 2	2010-04-27
Sidewall semiconductor transistors Grant 7,696,025 - Zhu , et al. April 13, 2	2010-04-13
Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain Grant 7,691,698 - Chidambarrao , et al. April 6, 2	2010-04-06
Semiconductor device structures incorporating voids and methods of fabricating such structures Grant 7,691,712 - Chidambarrao , et al. April 6, 2	2010-04-06
Stressed field effect transistors on hybrid orientation substrate Grant 7,687,829 - Chidambarrao , et al. March 30, 2	2010-03-30
Vertical Fin-FET MOS devices Grant 7,683,428 - Chidambarrao , et al. March 23, 2	2010-03-23
Semiconductor structure with enhanced performance using a simplified dual stress liner configuration Grant 7,675,118 - Chidambarrao , et al. March 9, 2	2010-03-09
System And Methodology For Determining Layout-dependent Effects In Ulsi Simulation App 20100050138 - Chidambarrao; Dureseti ; et al.	2010-02-25
Ic Having Viabar Interconnection And Related Method App 20100032846 - Chidambarrao; Dureseti ; et al.	2010-02-11
Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same Grant 7,659,160 - Belyansky , et al. February 9, 2	2010-02-09
Transistor with dielectric stressor element fully underlying the active semiconductor region Grant 7,659,581 - Chidambarrao , et al. February 9, 2	2010-02-09
Structure and method for MOSFET with reduced extension resistance Grant 7,655,972 - Chidambarrao , et al. February 2, 2	2010-02-02
Gate electrode stress control for finFET performance enhancement Grant 7,655,511 - Chidambarrao February 2, 2	2010-02-02
High Performance Stress-enhance Mosfet And Method Of Manufacture App 20100013024 - Chidambarrao; Dureseti ; et al.	2010-01-21
Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same Grant 7,648,871 - Belyansky , et al. January 19, 2	2010-01-19
Structure and method for making strained channel field effect transistor using sacrificial spacer Grant 7,645,656 - Chen , et al. January 12, 2	2010-01-12
Stressed SOI FET having tensile and compressive device regions Grant 7,632,724 - Chidambarrao , et al. December 15, 2	2009-12-15
Field effect transistors with dielectric source drain halo regions and reduced miller capacitance Grant 7,618,853 - Belyansky , et al. November 17, 2	2009-11-17
Embedded stressed nitride liners for CMOS performance improvement Grant 7,615,454 - Chidambarrao , et al. November 10, 2	2009-11-10
High performance stress-enhance MOSFET and method of manufacture Grant 7,615,418 - Chidambarrao , et al. November 10, 2	2009-11-10
High performance stress-enhance MOSFET and method of manufacture Grant 7,608,489 - Chidambarrao , et al. October 27, 2	2009-10-27
Intersect Area Based Ground Rule For Semiconductor Design App 20090265673 - Avanessian; Albrik ; et al.	2009-10-22
MOBILITY ENHANCEMENT IN SiGe HETEROJUNCTION BIPOLAR TRANSISTORS App 20090224286 - Adam; Thomas N. ; et al.	2009-09-10
Hybrid Orientation Scheme For Standard Orthogonal Circuits App 20090206412 - Chidambarrao; Dureseti	2009-08-20
Vertical Fin-fet Mos Devices App 20090200604 - Chidambarrao; Dureseti ; et al.	2009-08-13
CMOS device on hybrid orientation substrate comprising equal mobility for perpendicular devices of each type Grant 7,573,104 - Chidambarrao August 11, 2	2009-08-11
Silicon/silcion germaninum/silicon body device with embedded carbon dopant Grant 7,560,326 - Mocuta , et al. July 14, 2	2009-07-14
Strained Si on multiple materials for bulk or SOI substrates Grant 7,560,328 - Chidambarrao , et al. July 14, 2	2009-07-14
Methodology For Improving Device Performance Prediction From Effects Of Active Area Corner Rounding App 20090178012 - Chidambarrao; Dureseti ; et al.	2009-07-09
Compact Model Methodology For Pc Landing Pad Lithographic Rounding Impact On Device Performance App 20090177448 - Chidambarrao; Dureseti ; et al.	2009-07-09
Ca Resistance Variability Prediction Methodology App 20090171644 - Chidambarrao; Dureseti ; et al.	2009-07-02
Stress engineering using dual pad nitride with selective SOI device architecture Grant 7,550,364 - Chidambarrao , et al. June 23, 2	2009-06-23
Electrical fuse with a thinned fuselink middle portion Grant 7,550,323 - Chidambarrao , et al. June 23, 2	2009-06-23
Method And Structure For Semiconductor Devices With Silicon-germanium Deposits App 20090152590 - Adam; Thomas N. ; et al.	2009-06-18
Mobility enhancement in SiGe heterojunction bipolar transistors Grant 7,544,577 - Adam , et al. June 9, 2	2009-06-09
Method For Fabricating A Semiconductor Structure App 20090142894 - Zhu; Huilong ; et al.	2009-06-04
Automated Optimization Of Device Structure During Circuit Design Stage App 20090144670 - Chidambarrao; Dureseti ; et al.	2009-06-04
Curved FINFETs Grant 7,538,391 - Chidambarrao , et al. May 26, 2	2009-05-26
Structure and method for fabrication of deep junction silicon-on-insulator transistors Grant 7,534,667 - Chidambarrao , et al. May 19, 2	2009-05-19
Electrical Fuse Having A Fully Silicided Fuselink And Enhanced Flux Divergence App 20090108396 - Chidambarrao; Dureseti ; et al.	2009-04-30
Methods And System For Analysis And Management Of Parametric Yield App 20090106714 - Culp; James A. ; et al.	2009-04-23
Stress-generating Structure For Semiconductor-on-insulator Devices App 20090079026 - Zhu; Huilong ; et al.	2009-03-26
Method And Structure For Improving Device Performance Variation In Dual Stress Liner Technology App 20090079011 - Chidambarrao; Dureseti ; et al.	2009-03-26
Rotational shear stress for charge carrier mobility modification Grant 7,504,697 - Chidambarrao March 17, 2	2009-03-17
Strained dislocation-free channels for CMOS and method of manufacture Grant 7,495,291 - Chidambarrao , et al. February 24, 2	2009-02-24
Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers App 20090039461 - Henson; William K. ; et al.	2009-02-12
Electrical Fuse With A Thinned Fuselink Middle Portion App 20090042341 - Chidambarrao; Dureseti ; et al.	2009-02-12
Electrical Fuse With Enhanced Programming Current Divergence App 20090040006 - Chidambarrao; Dureseti ; et al.	2009-02-12
Stressed semiconductor device structures having granular semiconductor material Grant 7,488,658 - Doris , et al. February 10, 2	2009-02-10
After gate fabrication of field effect transistor having tensile and compressive regions Grant 7,485,519 - Chidambarrao , et al. February 3, 2	2009-02-03
Transistor having dielectric stressor elements at different depths from a semiconductor surface for applying shear stress Grant 7,476,938 - Chidambarrao , et al. January 13, 2	2009-01-13
Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon Grant 7,473,594 - Chakravarti , et al. January 6, 2	2009-01-06
Strained silicon on a SiGe on SOI substrate Grant 7,468,538 - Cheng , et al. December 23, 2	2008-12-23
Semiconductor devices having torsional stresses Grant 7,462,916 - Williams , et al. December 9, 2	2008-12-09
Method and structure for improving device performance variation in dual stress liner technology Grant 7,462,522 - Chidambarrao , et al. December 9, 2	2008-12-09
Ultra Thin Channel (UTC) MOSFET Structure Formed on BOX Regions Having Different Depths and Different Thicknesses Beneath the UTC and SourceDrain Regions and Method of Manufacture Thereof App 20080283918 - Cheng; Kangguo ; et al.	2008-11-20
Sidewall Semiconductor Transistors App 20080286909 - Zhu; Huilong ; et al.	2008-11-20
Formation of improved SOI substrates using bulk semiconductor wafers Grant 7,452,784 - Henson , et al. November 18, 2	2008-11-18
Structure and method for improved stress and yield in pFETS with embedded SiGe source/drain regions Grant 7,449,378 - Chidambarrao , et al. November 11, 2	2008-11-11
Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer Grant 7,446,350 - Chen , et al. November 4, 2	2008-11-04
Device having dual etch stop liner and reformed silicide layer and related methods Grant 7,446,062 - Chidambarrao , et al. November 4, 2	2008-11-04
Device having dual etch stop liner and protective layer Grant 7,446,395 - Chidambarrao , et al. November 4, 2	2008-11-04
Embedded Silicon Germanium Using A Double Buried Oxide Silicon-on-insulator Wafer App 20080265281 - Chen; Huajie ; et al.	2008-10-30
Structure And Method For Mosfet With Reduced Extension Resistance App 20080261369 - Chidambarrao; Dureseti ; et al.	2008-10-23
Cross-section Hourglass Shaped Channel Region For Charge Carrier Mobility Modification App 20080258180 - Chen; Huajie ; et al.	2008-10-23
Semiconductor Structure For Low Parasitic Gate Capacitance App 20080258234 - Henson; William K. ; et al.	2008-10-23
Low resistance contact semiconductor device structure Grant 7,439,123 - Chidambarrao , et al. October 21, 2	2008-10-21
Stressed Field Effect Transistors On Hybrid Orientation Substrate App 20080251817 - Chidambarrao; Dureseti ; et al.	2008-10-16
High performance CMOS device structures and method of manufacture Grant 7,436,029 - Doris , et al. October 14, 2	2008-10-14
Crystallographic Recess Etch For Embedded Semiconductor Region App 20080237634 - Dyer; Thomas W. ; et al.	2008-10-02
After Gate Fabrication Of Field Effect Transistor Having Tensile And Compressive Regions App 20080237709 - Chidambarrao; Dureseti ; et al.	2008-10-02
Stressed Soi Fet Having Tensile And Compressive Device Regions App 20080191281 - Chidambarrao; Dureseti ; et al.	2008-08-14
Semiconductor Device Stress Modeling Methodology App 20080195983 - Chidambarrao; Dureseti ; et al.	2008-08-14
Method for reduced N+ diffusion in strained Si on SiGe substrate Grant 7,410,846 - Chidambarrao , et al. August 12, 2	2008-08-12
N-fets With Tensilely Strained Semiconductor Channels, And Method For Fabricating Same Using Buried Pseudomorphic Layers App 20080179636 - Chidambarrao; Dureseti ; et al.	2008-07-31
Pseudomorphic Si/sige/si Body Device With Embedded Sige Source/drain App 20080179680 - CHIDAMBARRAO; Dureseti ; et al.	2008-07-31
Stressed field effect transistors on hybrid orientation substrate Grant 7,405,436 - Chidambarrao , et al. July 29, 2	2008-07-29
Efuse Containing Sige Stack App 20080169529 - Kim; Deok-Kee ; et al.	2008-07-17
Stressed Soi Fet Having Doped Glass Box Layer App 20080169508 - Chidambarrao; Dureseti ; et al.	2008-07-17
Structure And Method For Mobility Enhanced Mosfets With Unalloyed Silicide App 20080164491 - Liu; Yaocheng ; et al.	2008-07-10
Embedded Stressed Nitride Liners For Cmos Performance Improvement App 20080164532 - Chidambarrao; Dureseti ; et al.	2008-07-10
Curved Finfets App 20080164535 - Chidambarrao; Dureseti ; et al.	2008-07-10
Sidewall semiconductor transistors Grant 7,397,081 - Zhu , et al. July 8, 2	2008-07-08
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions Grant 7,396,714 - Chen , et al. July 8, 2	2008-07-08
Automated Optimization Of Vlsi Layouts For Regularity App 20080155482 - Chidambarrao; Dureseti ; et al.	2008-06-26
STRUCTURE AND METHOD FOR IMPROVED STRESS AND YIELD IN pFETS WITH EMBEDDED SiGe SOURCE/DRAIN REGIONS App 20080145986 - Chidambarrao; Dureseti ; et al.	2008-06-19
Strained finFET CMOS device structures Grant 7,388,259 - Doris , et al. June 17, 2	2008-06-17
Raised Sti Structure And Superdamascene Technique For Nmosfet Performance Enhancement With Embedded Silicon Carbon App 20080128712 - Chakravarti; Ashima B. ; et al.	2008-06-05
Stress inducing spacers Grant 7,374,987 - Chidambarrao , et al. May 20, 2	2008-05-20
Rotational Shear Stress For Charge Carrier Mobility Modification App 20080105953 - Chidambarrao; Dureseti	2008-05-08
Device Having Enhanced Stress State And Related Methods App 20080108228 - Chidambarrao; Dureseti ; et al.	2008-05-08
Embedded stressed nitride liners for CMOS performance improvement Grant 7,361,973 - Chidambarrao , et al. April 22, 2	2008-04-22
Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions Grant 7,358,551 - Chidambarrao , et al. April 15, 2	2008-04-15
Rotational shear stress for charge carrier mobility modification Grant 7,348,638 - Chidambarrao March 25, 2	2008-03-25
Device having enhanced stress state and related methods Grant 7,348,635 - Chidambarrao , et al. March 25, 2	2008-03-25
Creating Increased Mobility In A Bipolar Device App 20080067631 - Chidambarrao; Dureseti ; et al.	2008-03-20
Method for reduced N+ diffusion in strained Si on SiGe substrate Grant 7,345,329 - Chidambarrao , et al. March 18, 2	2008-03-18
Stressed Semiconductor Device Structures Having Granular Semiconductor Material App 20080064172 - Doris; Bruce B. ; et al.	2008-03-13
Field effect transistors with dielectric source drain halo regions and reduced miller capacitance Grant 7,342,266 - Belyansky , et al. March 11, 2	2008-03-11
Method And Structure For Improving Device Performance Variation In Dual Stress Liner Technology App 20080057653 - Chidambarrao; Dureseti ; et al.	2008-03-06
Semiconductor Structure With Enhanced Performance Using A Simplified Dual Stress Liner Configuration App 20080054357 - Chidambarrao; Dureseti ; et al.	2008-03-06
Semiconductor Structure Including Multiple Stressed Layers App 20080050863 - Henson; William K. ; et al.	2008-02-28
Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models Grant 7,337,420 - Chidambarrao , et al. February 26, 2	2008-02-26
Field Effect Transistors (fets) With Inverted Source/drain Metallic Contacts, And Method Of Fabricating Same App 20080042174 - Belyansky; Michael P. ; et al.	2008-02-21
Embedded Stressed Nitride Liners For Cmos Performance Improvement App 20080044974 - Chidambarrao; Dureseti ; et al.	2008-02-21
Design Structure Incorporating Semiconductor Device Structures with Voids App 20080040697 - Chidambarrao; Dureseti ; et al.	2008-02-14
Creating increased mobility in a bipolar device Grant 7,329,941 - Chidambarrao , et al. February 12, 2	2008-02-12
Raised Sti Structure And Superdamascene Technique For Nmosfet Performance Enhancement With Embedded Silicon Carbon App 20080026516 - Chakravarti; Ashima B. ; et al.	2008-01-31
High Performance Cmos Device Structures And Method Of Manufacture App 20080026522 - Doris; Bruce B. ; et al.	2008-01-31
Semiconductor Devices Having Torsional Stresses App 20080020531 - Williams; Richard Q. ; et al.	2008-01-24
Field Effect Transistors With Dielectric Source Drain Halo Regions And Reduced Miller Capacitance App 20080020522 - Belyansky; Michael P. ; et al.	2008-01-24
Semiconductor Device Structures Incorporating Voids and Methods of Fabricating Such Structures App 20070296039 - Chidambarrao; Dureseti ; et al.	2007-12-27
High Performance Stress-enhanced Mosfets Using Si:c And Sige Epitaxial Source/drain And Method Of Manufacture App 20070296038 - CHEN; Huajie ; et al.	2007-12-27
Device Having Dual Etch Stop Liner And Reformed Silicide Layer And Related Methods App 20070296044 - Chidambarrao; Dureseti ; et al.	2007-12-27
Multiple Conduction State Devices Having Differently Stressed Liners App 20070296001 - Chidambarrao; Dureseti ; et al.	2007-12-27
Dual stressed SOI substrates Grant 7,312,134 - Chidambarrao , et al. December 25, 2	2007-12-25
Device Having Dual Etch Stop Liner And Protective Layer App 20070292696 - Chidambarrao; Dureseti ; et al.	2007-12-20
Method for forming dual etch stop liner and protective layer in a semiconductor device Grant 7,306,983 - Chidambarrao , et al. December 11, 2	2007-12-11
High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture Grant 7,303,949 - Chen , et al. December 4, 2	2007-12-04
Optimized Deep Source/drain Junctions With Thin Poly Gate In A Field Effect Transistor App 20070275532 - Chidambarrao; Dureseti ; et al.	2007-11-29
Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers App 20070275537 - Henson; William K. ; et al.	2007-11-29
Method of making strained channel CMOS transistors having lattice-mismatched epitaxial Grant 7,297,583 - Chen , et al. November 20, 2	2007-11-20
Method for reduced N+ diffusion in strained Si on SiGe substrate Grant 7,297,601 - Chidambarrao , et al. November 20, 2	2007-11-20
High Performance Stress-enhanced Mosfets Using Si:c And Sige Epitaxial Source/drain And Method Of Manufacture App 20070264783 - CHEN; Huajie ; et al.	2007-11-15
Silicon/silcion Germaninum/silicon Body Device With Embedded Carbon Dopant App 20070257249 - Mocuta; Anda C. ; et al.	2007-11-08
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions Grant 7,291,528 - Chen , et al. November 6, 2	2007-11-06
High Performance Stress-enhance Mosfet And Method Of Manufacture App 20070254423 - Chidambarrao; Dureseti ; et al.	2007-11-01
High Performance Stress-enhance Mosfet And Method Of Manufacture App 20070254422 - Chidambarrao; Dureseti ; et al.	2007-11-01
A Structure And Method For Fabrication Of Deep Junction Silicon-on-insulator Transistors App 20070249126 - Chidambarrao; Dureseti ; et al.	2007-10-25
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions App 20070249114 - Chen; Huajie ; et al.	2007-10-25
High performance CMOS device structures and method of manufacture Grant 7,279,746 - Doris , et al. October 9, 2	2007-10-09
Silicon Device On Si: C-oi And Sgoi And Method Of Manufacture App 20070228472 - Chidambarrao; Dureseti ; et al.	2007-10-04
Silicon Device On Si: C-oi And Sgoi And Method Of Manufacture App 20070231979 - CHIDAMBARRAO; Dureseti ; et al.	2007-10-04
Enhanced PFET using shear stress Grant 7,274,084 - Chidambarrao September 25, 2	2007-09-25
Laser Surface Annealing Of Antimony Doped Amorphized Semiconductor Region App 20070212861 - Chidambarrao; Dureseti ; et al.	2007-09-13
Hybrid Orientation Scheme For Standard Orthogonal Circuits App 20070205460 - Chidambarrao; Dureseti	2007-09-06
Dual Stressed Soi Substrates App 20070202639 - Chidambarrao; Dureseti ; et al.	2007-08-30
Dual stressed SOI substrates Grant 7,262,087 - Chidambarrao , et al. August 28, 2	2007-08-28
Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain App 20070196987 - Chidambarrao; Dureseti ; et al.	2007-08-23
Mosfet Wth High Angle Sidewall Gate And Contacts For Reduced Miller Capacitance App 20070184621 - Chidambarrao; Dureseti ; et al.	2007-08-09
Silicon device on Si:C-OI and SGOI and method of manufacture Grant 7,247,534 - Chidambarrao , et al. July 24, 2	2007-07-24
STRAINED Si ON MULTIPLE MATERIALS FOR BULK OR SOI SUBSTRATES App 20070166897 - Chidambarrao; Dureseti ; et al.	2007-07-19
Semiconductor Device Structure Having Low And High Performance Devices Of Same Conductive Type On Same Substrate App 20070158753 - Arnold; John C. ; et al.	2007-07-12
Field Effect Transistors With Dielectric Source Drain Halo Regions And Reduced Miller Capacitance App 20070161169 - Belyansky; Michael P. ; et al.	2007-07-12
Programming and determining state of electrical fuse using field effect transistor having multiple conduction states Grant 7,242,239 - Hanson , et al. July 10, 2	2007-07-10
Stress Engineering Using Dual Pad Nitride With Selective Soi Device Architecture App 20070122965 - Chidambarrao; Dureseti ; et al.	2007-05-31
Transistor With Dielectric Stressor Element Fully Underlying The Active Semiconductor Region App 20070122956 - Chidambarrao; Dureseti ; et al.	2007-05-31
MOSFET with high angle sidewall gate and contacts for reduced miller capacitance Grant 7,224,021 - Chidambarrao , et al. May 29, 2	2007-05-29
Strained Si on multiple materials for bulk or SOI substrates Grant 7,223,994 - Chidambarrao , et al. May 29, 2	2007-05-29
Structure And Method For Mosfet With Reduced Extension Resistance App 20070114611 - Chidambarrao; Dureseti ; et al.	2007-05-24
Transistor Having Dielectric Stressor Elements At Different Depths From A Semiconductor Surface For Applying Shear Stress App 20070114632 - Chidambarrao; Dureseti ; et al.	2007-05-24
Transistor having dielectric stressor elements for applying in-plane shear stress Grant 7,221,024 - Chidambarrao , et al. May 22, 2	2007-05-22
Rotational Shear Stress For Charge Carrier Mobility Modification App 20070108531 - Chidambarrao; Dureseti	2007-05-17
Gate Electrode Stress Control For Finfet Performance Enhancement App 20070096206 - Chidambarrao; Dureseti	2007-05-03
Transistor Having Dielectric Stressor Elements For Applying In-plane Shear Stress App 20070096223 - Chidambarrao; Dureseti ; et al.	2007-05-03
Low resistance contact semiconductor device structure App 20070099362 - Chidambarrao; Dureseti ; et al.	2007-05-03
Low Modulus Spacers For Channel Stress Enhancement App 20070096170 - Chidambarrao; Dureseti ; et al.	2007-05-03
Transistor With Dielectric Stressor Elements App 20070096215 - Chidambarrao; Dureseti ; et al.	2007-05-03
Field Effect Transistors (fets) With Inverted Source/drain Metallic Contacts, And Method Of Fabricating Same App 20070092990 - Belyansky; Michael P. ; et al.	2007-04-26
Reduction of boron diffusivity in pfets App 20070093030 - Buehrer; Frederick William ; et al.	2007-04-26
Stress engineering using dual pad nitride with selective SOI device architecture Grant 7,202,513 - Chidambarrao , et al. April 10, 2	2007-04-10
Strained finFETs and method of manufacture Grant 7,198,995 - Chidambarrao , et al. April 3, 2	2007-04-03
Stress Engineering Using Dual Pad Nitride With Selective Soi Device Architecture App 20070069294 - Chidambarrao; Dureseti ; et al.	2007-03-29
Planar Ultra-thin Semiconductor-on-insulator Channel Mosfet With Embedded Source/drain App 20070069300 - Cheng; Kangguo ; et al.	2007-03-29
Trench capacitor DRAM cell using buried oxide as array top oxide Grant 7,195,972 - Chidambarrao , et al. March 27, 2	2007-03-27
Multiple Low And High K Gate Oxides On Single Gate For Lower Miller Capacitance And Improved Drive Current App 20070063277 - Belyansky; Michael P. ; et al.	2007-03-22
Mosfet With High Angle Sidewall Gate And Contacts For Reduced Miller Capacitance App 20070057334 - Chidambarrao; Dureseti ; et al.	2007-03-15
Mobility enhancement in SiGe heterojunction bipolar transistors App 20070045775 - Adam; Thomas N. ; et al.	2007-03-01
In situ doped embedded sige extension and source/drain for enhanced PFET performance Grant 7,176,481 - Chen , et al. February 13, 2	2007-02-13
Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models App 20070028195 - Chidambarrao; Dureseti ; et al.	2007-02-01
Structure of vertical strained silicon devices Grant 7,170,126 - Cheng , et al. January 30, 2	2007-01-30
STRUCTURE AND METHOD FOR IMPROVED STRESS AND YIELD IN pFETS WITH EMBEDDED SiGe SOURCE/DRAIN REGIONS App 20070018205 - Chidambarrao; Dureseti ; et al.	2007-01-25
Structure And Method For Making Strained Channel Field Effect Transistor Using Sacrificial Spacer App 20060292779 - Chen; Huajie ; et al.	2006-12-28
Programming And Determining State Of Electrical Fuse Using Field Effect Transistor Having Multiple Conduction States App 20060273841 - Hanson; David R. ; et al.	2006-12-07
Structure And Method Of Making Field Effect Transistor Having Multiple Conduction States App 20060273393 - Chidambarrao; Dureseti ; et al.	2006-12-07
NFETs using gate induced stress modulation Grant 7,144,767 - Chidambarrao , et al. December 5, 2	2006-12-05
Embedded Silicon Germanium Using A Double Buried Oxide Silicon-on-insulator Wafer App 20060255330 - Chen; Huajie ; et al.	2006-11-16
Gate controlled floating well vertical MOSFET App 20060258060 - Chen; Xiangdong ; et al.	2006-11-16
Structure and method for making strained channel field effect transistor using sacrificial spacer Grant 7,135,724 - Chen , et al. November 14, 2	2006-11-14
Out of the box vertical transistor for eDRAM on SOI Grant 7,129,130 - Adkisson , et al. October 31, 2	2006-10-31
Sense amplifier including multiple conduction state field effect transistor Grant 7,123,529 - Hanson , et al. October 17, 2	2006-10-17
Stressed semiconductor device structures having granular semiconductor material Grant 7,122,849 - Doris , et al. October 17, 2	2006-10-17
Gate controlled floating well vertical MOSFET Grant 7,102,914 - Chen , et al. September 5, 2	2006-09-05
Bipolar transistor with extrinsic stress layer Grant 7,102,205 - Chidambarrao , et al. September 5, 2	2006-09-05
Method and structure for improved MOSFETs using poly/silicide gate height control Grant 7,091,563 - Chidambarrao , et al. August 15, 2	2006-08-15
Structure And Method To Enhance Stress In A Channel Of Cmos Devices Using A Thin Gate App 20060160317 - Zhu; Huilong ; et al.	2006-07-20
Enhanced Pfet Using Shear Stress App 20060151838 - Chidambarrao; Dureseti	2006-07-13
In Situ Doped Embedded Sige Extension And Source/drain For Enhanced Pfet Performance App 20060151837 - Chen; Huajie ; et al.	2006-07-13
NFETs using gate induced stress modulation App 20060145274 - Chidambarrao; Dureseti ; et al.	2006-07-06
Stressed field effect transistors on hybrid orientation substrate App 20060145264 - Chidambarrao; Dureseti ; et al.	2006-07-06
Dual Stressed Soi Substrates App 20060125008 - Chidambarrao; Dureseti ; et al.	2006-06-15
Sidewall Semiconductor Transistors App 20060124993 - Zhu; Huilong ; et al.	2006-06-15
Device Having Enhanced Stress State And Related Methods App 20060128091 - Chidambarrao; Dureseti ; et al.	2006-06-15
Device Having Dual Etch Stop Liner And Protective Layer And Related Methods App 20060128086 - Chidambarrao; Dureseti ; et al.	2006-06-15
Device Having Dual Etch Stop Liner And Reformed Silicide Layer And Related Methods App 20060128145 - Chidambarrao; Dureseti ; et al.	2006-06-15
Lowered Source/Drain Transistors App 20060108651 - Zhu; Huilong ; et al.	2006-05-25
Out of the box vertical transistor for eDRAM on SOI App 20060091442 - Adkisson; James W. ; et al.	2006-05-04
Method for reduced N+ diffusion in strained Si on SiGe substrate App 20060073649 - Chidambarrao; Dureseti ; et al.	2006-04-06
Structure And Method For Making Strained Channel Field Effect Transistor Using Sacrificial Spacer App 20060065914 - Chen; Huajie ; et al.	2006-03-30
Strained finfet cmos device structures App 20060057787 - Doris; BruceB ; et al.	2006-03-16
Bipolar transistor with extrinsic stress layer App 20060043529 - Chidambarrao; Dureseti ; et al.	2006-03-02
Creating Increased Mobility In A Bipolar Device App 20060019458 - Chidambarrao; Dureseti ; et al.	2006-01-26
Isolation structures for imposing stress patterns App 20050280051 - Chidambarrao, Dureseti ; et al.	2005-12-22
Structure and method to improve channel mobility by gate electrode stress modification App 20050282325 - Belyansky, Michael P. ; et al.	2005-12-22
Strained Si on multiple materials for bulk or SOI substrates App 20050269561 - Chidambarrao, Dureseti ; et al.	2005-12-08
Embedded stressed nitride liners for CMOS performance improvement App 20050258515 - Chidambarrao, Dureseti ; et al.	2005-11-24
MOSFET structure with high mechanical stress in the channel App 20050260808 - Chen, Xiangdong ; et al.	2005-11-24
OUT OF THE BOX VERTICAL TRANSISTOR FOR eDRAM ON SOI App 20050247966 - Adkisson, James W. ; et al.	2005-11-10
Structure and method to improve channel mobility by gate electrode stress modification App 20050245017 - Belyansky, Michael P. ; et al.	2005-11-03
Strained silicon NMOS devices with embedded source/drain App 20050242340 - Chidambarrao, Dureseti ; et al.	2005-11-03
Gate Controlled Floating Well Vertical Mosfet App 20050190590 - Chen, Xiangdong ; et al.	2005-09-01
Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby App 20050191795 - Chidambarrao, Dureseti ; et al.	2005-09-01
Strained silicon on relaxed sige film with uniform misfit dislocation density App 20050164477 - Chidambarrao, Dureseti ; et al.	2005-07-28
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions App 20050158931 - Chen, Huajie ; et al.	2005-07-21
High performance strained silicon FinFETs device and method for forming same App 20050145941 - Bedell, Stephen W. ; et al.	2005-07-07
Method for reduced N+ diffusion in strained Si on SiGe substrate App 20050145992 - Chidambarrao, Dureseti ; et al.	2005-07-07
Method and structure for improved MOSFETs using poly/silicide gate height control App 20050145950 - Chidambarrao, Dureseti ; et al.	2005-07-07
Method of making strained channel CMOS transistors having lattice-mismatched epitaxial App 20050148133 - Chen, Huaje ; et al.	2005-07-07
CMOS performance enhancement using localized voids and extended defects App 20050148134 - Dokumaci, Omer H. ; et al.	2005-07-07
Strained dislocation-free channels for CMOS and method of manufacture App 20050139930 - Chidambarrao, Dureseti ; et al.	2005-06-30
MOSFET performance improvement using deformation in SOI structure App 20050142788 - Chidambarrao, Dureseti ; et al.	2005-06-30
Strained silicon on a SiGe on SOI substrate App 20050142700 - Cheng, Kangguo ; et al.	2005-06-30