Chidambaram; PR

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chidambaram; PR.The latest application filed is for "system and method of varying gate lengths of multiple cores".

Company Profile

0.25.43

Chidambaram; PR - San Diego CA
CHIDAMBARAM; PR - Richardson TX
Chidambaram, PR. - Richardson TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Capacitor using middle of line (MOL) conductive layers Grant 9,496,254 - Chidambaram , et al. November 15, 2	2016-11-15
System and method of varying gate lengths of multiple cores Grant 9,461,040 - Cai , et al. October 4, 2	2016-10-04
Bone frame, low resistance via coupled metal oxide-metal (MOM) orthogonal finger capacitor Grant 9,269,492 - Zhu , et al. February 23, 2	2016-02-23
Transistor with a diffusion barrier Grant 9,263,522 - Yang , et al. February 16, 2	2016-02-16
Complementary back end of line (BEOL) capacitor Grant 9,252,104 - Zhu , et al. February 2, 2	2016-02-02
FinFET with backgate, without punchthrough, and with reduced fin height variation Grant 9,236,483 - Yang , et al. January 12, 2	2016-01-12
System And Method Of Varying Gate Lengths Of Multiple Cores App 20150311198 - Cai; Ming ; et al.	2015-10-29
Back End Of Line (beol) Local Optimization To Improve Product Performance App 20150303145 - ZHU; John Jianhong ; et al.	2015-10-22
Capacitor Using Middle Of Line (mol) Conductive Layers App 20150221638 - Chidambaram; PR ; et al.	2015-08-06
System and method of varying gate lengths of multiple cores Grant 9,076,775 - Cai , et al. July 7, 2	2015-07-07
System And Method Of Manufacturing A Fin Field-effect Transistor Having Multiple Fin Heights App 20150162404 - Yang; Bin ; et al.	2015-06-11
Transistor With A Diffusion Barrier App 20150162405 - Yang; Bin ; et al.	2015-06-11
Local interconnect structures for high density Grant 9,024,418 - Zhu , et al. May 5, 2	2015-05-05
Capacitor using middle of line (MOL) conductive layers Grant 9,012,966 - Chidambaram , et al. April 21, 2	2015-04-21
Semiconductor Device Having High Mobility Channel App 20150091060 - Yang; Bin ; et al.	2015-04-02
System And Method Of Varying Gate Lengths Of Multiple Cores App 20150061037 - Cai; Ming ; et al.	2015-03-05
Complementary Back End Of Line (beol) Capacitor App 20150028452 - ZHU; John J. ; et al.	2015-01-29
Cmos Technology Integration App 20150001631 - LI; Xia ; et al.	2015-01-01
Metal Oxide Semiconductor (mos) Isolation Schemes With Continuous Active Areas Separated By Dummy Gates And Related Methods App 20140264610 - Yang; Bin ; et al.	2014-09-18
Complementary Back End Of Line (beol) Capacitor App 20140231957 - Zhu; John J. ; et al.	2014-08-21
Metal-insulator-metal Capacitor Under Redistribution Layer App 20140225224 - Zhu; John J. ; et al.	2014-08-14
Metal-insulator-metal Capacitor Over Conductive Layer App 20140225223 - Zhu; John J. ; et al.	2014-08-14
Spiral Metal-on-metal (smom) Capacitors, And Related Systems And Methods App 20140203404 - Choi; Jihong ; et al.	2014-07-24
Resistor And Resistor Fabrication For Semiconductor Devices App 20140197520 - Choi; Jihong ; et al.	2014-07-17
Mim Capacitor And Mim Capacitor Fabrication For Semiconductor Devices App 20140197519 - Choi; Jihong ; et al.	2014-07-17
Capacitor Using Middle Of Line (mol) Conductive Layers App 20140138793 - Chidambaram; PR ; et al.	2014-05-22
Bone Frame, Low Resistance Via Coupled Metal Oxide-metal (mom) Orthogonal Finger Capacitor App 20140092523 - Zhu; John J. ; et al.	2014-04-03
Standard cell architecture using double poly patterning for multi VT devices Grant 8,610,176 - Patel , et al. December 17, 2	2013-12-17
Metal Finger Capacitors With Hybrid Metal Finger Orientations In Stack With Unidirectional Metal Layers App 20130320494 - Zhu; John J. ; et al.	2013-12-05
Standard Cell Architecture Using Double Poly Patterning for Multi VT Devices App 20120180016 - Chidambaram; PR ; et al.	2012-07-12
Nitrogen Based Implants for Defect Reduction in Strained Silicon App 20100120215 - CHAKRAVARTHI; Srinivasan ; et al.	2010-05-13
Nitrogen based implants for defect reduction in strained silicon Grant 7,670,892 - Chakravarthi , et al. March 2, 2	2010-03-02
Methods, Systems and Structures for Forming Semiconductor Structures Incorporating High-Temperature Processing Steps App 20090224296 - Chidambaram; PR ; et al.	2009-09-10
Drain extended MOS transistors and methods for making the same Grant 7,560,324 - Chidambaram July 14, 2	2009-07-14
Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel Grant 7,339,215 - Chidambaram March 4, 2	2008-03-04
Drive current improvement from recessed SiGe incorporation close to gate Grant 7,244,654 - Chidambaram , et al. July 17, 2	2007-07-17
Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel App 20070132027 - Chidambaram; PR	2007-06-14
Transistor fabrication methods using dual sidewall spacers Grant 7,217,626 - Bu , et al. May 15, 2	2007-05-15
Nitrogen based implants for defect reduction in strained silicon App 20070105294 - Chakravarthi; Srinivasan ; et al.	2007-05-10
Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel Grant 7,208,362 - Chidambaram April 24, 2	2007-04-24
Methods, systems and structures for forming improved transistors Grant 7,122,435 - Chidambaram , et al. October 17, 2	2006-10-17
System and method for improved dopant profiles in CMOS transistors Grant 7,118,977 - Chidambaram , et al. October 10, 2	2006-10-10
Versatile system for limiting electric field degradation of semiconductor structures Grant 7,101,751 - Chidambaram , et al. September 5, 2	2006-09-05
Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps App 20060172502 - Chidambaram; PR ; et al.	2006-08-03
Forming a retrograde well in a transistor to enhance performance of the transistor Grant 7,061,058 - Chakravarthi , et al. June 13, 2	2006-06-13
Increased drive current by isotropic recess etch Grant 7,060,579 - Chidambaram , et al. June 13, 2	2006-06-13
System and method for improved dopant profiles in CMOS transistors App 20060099744 - Chidambaram; PR ; et al.	2006-05-11
Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation App 20060068541 - Chidambaram; PR ; et al.	2006-03-30
Transistor fabrication methods using reduced width sidewall spacers Grant 7,012,028 - Bu , et al. March 14, 2	2006-03-14
Increased drive current by isotropic recess etch App 20060024898 - Chidambaram; PR ; et al.	2006-02-02
Methods, systems and structures for forming improved transistors App 20060024876 - Chidambaram; PR ; et al.	2006-02-02
Transistor fabrication methods using reduced width sidewall spacers App 20060019455 - Bu; Haowen ; et al.	2006-01-26
Transistor fabrication methods using dual sidewall spacers App 20060019456 - Bu; Haowen ; et al.	2006-01-26
Drain extended MOS transistors and methods for making the same App 20060006461 - Chidambaram; Pr	2006-01-12
Versatile system for limiting electric field degradation of semiconductor structures App 20050258494 - Chidambaram, PR ; et al.	2005-11-24
Versatile system for limiting electric field degradation of semiconductor structures App 20050260858 - Chidambaram, PR ; et al.	2005-11-24
Forming a retrograde well in a transistor to enhance performance of the transistor Grant 6,927,137 - Chakravarthi , et al. August 9, 2	2005-08-09
Drive current improvement from recessed SiGe incorporation close to gate App 20050139872 - Chidambaram, Pr ; et al.	2005-06-30
Forming a retrograde well in a transistor to enhance performance of the transistor App 20050118792 - Chakravarthi, Srinivasan ; et al.	2005-06-02
Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel App 20040262694 - Chidambaram, PR	2004-12-30
System and method for depositing a graded carbon layer to enhance critical layer stability App 20040248354 - Chidambaram, Pr ; et al.	2004-12-09
System and method for depositing a graded carbon layer to enhance critical layer stability App 20040235228 - Chidambaram, PR. ; et al.	2004-11-25
Method for producing low/high voltage threshold transistors in semiconductor processing Grant 6,818,518 - Chidambaram November 16, 2	2004-11-16
Semiconductor structure and method of fabrication App 20040191999 - Chidambaram, Pr ; et al.	2004-09-30
Process for retarding lateral diffusion of phosphorous App 20040031970 - Chakravarthi, Srinivasan ; et al.	2004-02-19
Versatile system for PMOS I/O transistor integration App 20030124790 - Chidambaram, PR	2003-07-03
Method of providing polysilicon spacer for implantation App 20030008482 - Chidambaram, PR	2003-01-09

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.