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Patent applications and USPTO patent grants for Chidambaram; Periannan R..The latest application filed is for "reduction of sti corner defects during spe in semiconductor device fabrication using dsb substrate and hot technology".
Patent | Date |
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Reduction of STI corner defects during SPE in semiconductor device fabrication using DSB substrate and hot technology Grant 8,846,487 - Pinto , et al. September 30, 2 | 2014-09-30 |
Reduction Of Sti Corner Defects During Spe In Semiconductor Device Fabrication Using Dsb Substrate And Hot Technology App 20130029471 - Pinto; Angelo ;   et al. | 2013-01-31 |
Reduction Of Sti Corner Defects During Spe In Semicondcutor Device Fabrication Using Dsb Substrate And Hot Technology App 20100304547 - Pinto; Angelo ;   et al. | 2010-12-02 |
Method To Reduce Residual Sti Corner Defects Generated During Spe In The Fabrication Of Nano-scale Cmos Transistors Using Dsb Substrate And Hot Technology App 20090057816 - Pinto; Angelo ;   et al. | 2009-03-05 |
Phosphorus activated NMOS using SiC process Grant 7,179,696 - Chakravarthi , et al. February 20, 2 | 2007-02-20 |
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