Chiang; Mu-Chi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chiang; Mu-Chi.The latest application filed is for "isolation structure for isolating epitaxially grown source/drain regions and method of fabrication thereof".

Company Profile

2.29.27

Chiang; Mu-Chi - Hsinchu TW
Chiang; Mu-Chi - Hsin-Chu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Isolation Structure For Isolating Epitaxially Grown Source/Drain Regions And Method Of Fabrication Thereof App 20220293752 - Lin; Ta-Chun ; et al.	2022-09-15
Isolation Structure For Preventing Unintentional Merging Of Epitaxially Grown Source/Drain App 20220246613 - Lin; Ta-Chun ; et al.	2022-08-04
Isolation structure for for isolating epitaxially grown source/drain regions and method of fabrication thereof Grant 11,349,002 - Lin , et al. May 31, 2	2022-05-31
Isolation structure for preventing unintentional merging of epitaxially grown source/drain Grant 11,315,924 - Lin , et al. April 26, 2	2022-04-26
Isolation Structure for for Isolating Epitaxially Grown Source/Drain Regions and Method of Fabrication Thereof App 20220102509 - Lin; Ta-Chun ; et al.	2022-03-31
Isolation Structure for Preventing Unintentional Merging of Epitaxially Grown Source/Drain App 20210408000 - Lin; Ta-Chun ; et al.	2021-12-30
Substrate resistor and method of making same Grant 10,872,963 - Chen , et al. December 22, 2	2020-12-22
Substrate Resistor and Method of Making Same App 20190280097 - Chen; Hua Feng ; et al.	2019-09-12
Substrate resistor and method of making same Grant 10,297,669 - Chen , et al.	2019-05-21
Semiconductor device with biased feature Grant 9,607,835 - Liu , et al. March 28, 2	2017-03-28
Substrate Resistor and Method of Making Same App 20170062578 - Chen; Hua Feng ; et al.	2017-03-02
Substrate resistor and method of making same Grant 9,496,325 - Chen , et al. November 15, 2	2016-11-15
FinFETs and methods for forming the same Grant 9,466,696 - Mor , et al. October 11, 2	2016-10-11
Control fin heights in FinFET structures Grant 9,460,970 - Mor , et al. October 4, 2	2016-10-04
Semiconductor Device With Biased Feature App 20150357460 - Liu; Chia-Chu ; et al.	2015-12-10
Semiconductor device with biased feature Grant 9,059,001 - Liu , et al. June 16, 2	2015-06-16
Control Fin Heights in FinFET Structures App 20150155208 - Mor; Yi-Shien ; et al.	2015-06-04
Control fin heights in FinFET structures Grant 8,975,698 - Mor , et al. March 10, 2	2015-03-10
Field effect transistors and method of forming the same Grant 8,969,922 - Liu , et al. March 3, 2	2015-03-03
FinFET design with LDD extensions Grant 8,865,560 - Mor , et al. October 21, 2	2014-10-21
Control Fin Heights in FinFET Structures App 20140103453 - Mor; Yi-Shien ; et al.	2014-04-17
Control fin heights in FinFET structures Grant 8,659,097 - Mor , et al. February 25, 2	2014-02-25
Substrate Resistor and Method of Making Same App 20130341731 - Chen; Hua Feng ; et al.	2013-12-26
FinFET Design with LDD Extensions App 20130228876 - Mor; Yi-Shien ; et al.	2013-09-05
Semiconductor Device and Method of Forming the Same App 20130200461 - Liu; Chia-Chu ; et al.	2013-08-08
FinFETs and Methods for Forming the Same App 20130187206 - Mor; Yi-Shien ; et al.	2013-07-25
Control Fin Heights in FinFET Structures App 20130181300 - Mor; Yi-Shien ; et al.	2013-07-18
Semiconductor Device With Biased Feature App 20130154004 - Liu; Chia-Chu ; et al.	2013-06-20
Semiconductor device and fabrication thereof Grant 8,421,166 - Chi , et al. April 16, 2	2013-04-16
Semiconductor Device And Fabrication Thereof App 20110260220 - CHI; Min-Hwa ; et al.	2011-10-27
Semiconductor device and fabrication thereof Grant 7,994,040 - Chi , et al. August 9, 2	2011-08-09
Source and drain structures and manufacturing methods Grant 7,649,226 - Liaw , et al. January 19, 2	2010-01-19
Quasi-plannar and FinFET-like transistors on bulk silicon Grant 7,564,105 - Chi , et al. July 21, 2	2009-07-21
Semiconductor device and fabrication thereof App 20080254579 - Chi; Min-Hwa ; et al.	2008-10-16
Source and drain structures and manufacturing methods App 20080185665 - Liaw; Jhon-Jhy ; et al.	2008-08-07
Amorphous carbon contact film for contact hole etch process Grant 7,371,634 - Chiang , et al. May 13, 2	2008-05-13
Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a Teos liner deposition Grant RE40,138 - Chiang , et al. March 4, 2	2008-03-04
Amorphous carbon contact film for contact hole etch process App 20060170058 - Chiang; Wen-Chuan ; et al.	2006-08-03
Quasi-plannar and FinFET-like transistors on bulk silicon App 20050239254 - Chi, Min-Hwa ; et al.	2005-10-27
Novel formation of an aluminum contact pad free of plasma induced damage by applying CMP App 20040175918 - Niu, Pao-Kang ; et al.	2004-09-09
Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect Grant 6,500,739 - Wang , et al. December 31, 2	2002-12-31
Method of forming an indium retrograde profile via use of a low temperature anneal procedure to reduce NMOS short channel effects Grant 6,368,928 - Wang , et al. April 9, 2	2002-04-09
Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a teos liner deposition Grant 6,235,600 - Chiang , et al. May 22, 2	2001-05-22

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