| Patent | Date |
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Method of forming layout design
Grant 9,899,263 - Hsieh , et al. February 20, 2 | 2018-02-20 |
Jog design in integrated circuits
Grant 9,691,721 - Wu , et al. June 27, 2 | 2017-06-27 |
Semiconductor structure and manufacturing method thereof
Grant 9,570,584 - Lin , et al. February 14, 2 | 2017-02-14 |
Jog Design in Integrated Circuits
App 20160276297 - Wu; Tsung-Lin ; et al. | 2016-09-22 |
Method of Forming Layout Design
App 20160254190 - Hsieh; Tung-Heng ; et al. | 2016-09-01 |
Jog design in integrated circuits
Grant 9,355,912 - Wu , et al. May 31, 2 | 2016-05-31 |
Method of forming layout design
Grant 9,336,348 - Hsieh , et al. May 10, 2 | 2016-05-10 |
Method Of Forming Layout Design
App 20160078164 - HSIEH; Tung-Heng ; et al. | 2016-03-17 |
Semiconductor Structure And Manufacturing Method Thereof
App 20160049464 - LIN; CHIH HSIUNG ; et al. | 2016-02-18 |
Jog Design in Integrated Circuits
App 20150087143 - Wu; Tsung-Lin ; et al. | 2015-03-26 |
Jog design in integrated circuits
Grant 8,901,627 - Wu , et al. December 2, 2 | 2014-12-02 |
Jog Design in Integrated Circuits
App 20140138750 - Wu; Tsung-Lin ; et al. | 2014-05-22 |
Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor
Grant 7,622,347 - Chiang , et al. November 24, 2 | 2009-11-24 |
Integrating a DRAM with an SRAM having butted contacts and resulting devices
App 20080116496 - Tzeng; Kuo-Chyuan ; et al. | 2008-05-22 |
Method to reduce a capacitor depletion phenomena
Grant 7,332,394 - Chiang February 19, 2 | 2008-02-19 |
Method of forming one-transistor memory cell and structure formed thereby
Grant 7,238,566 - Chiang July 3, 2 | 2007-07-03 |
Self-aligned Metal Electrode To Eliminate Native Oxide Effect For Metal Insulator Semiconductor (mis) Capacitor
App 20070111438 - Chiang; Min-Hsiung ; et al. | 2007-05-17 |
Dual poly layer and method of manufacture
Grant 7,208,369 - Pai , et al. April 24, 2 | 2007-04-24 |
Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor
Grant 7,180,116 - Chiang , et al. February 20, 2 | 2007-02-20 |
Method to reduce a capacitor depletion phenomena
App 20060057803 - Chiang; Min-Hsiung | 2006-03-16 |
Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor
App 20050272217 - Chiang, Min-Hsiung ; et al. | 2005-12-08 |
Method to reduce a capacitor depletion phenomena
App 20050151180 - Chiang, Min-Hsiung | 2005-07-14 |
Method to form a robust TiCI4 based CVD TiN film
App 20050112876 - Wu, Chih-Ta ; et al. | 2005-05-26 |
Method of forming one-transistor memory cell and structure formed thereby
App 20050077557 - Chiang, Min-Hsiung | 2005-04-14 |
Dual poly layer and method of manufacture
App 20050056885 - Pai, Chih-Yang ; et al. | 2005-03-17 |
Method for integrating copper process and MIM capacitor for embedded DRAM
Grant 6,849,387 - Chiang , et al. February 1, 2 | 2005-02-01 |
Method for forming high purity silicon oxide field oxide isolation region
Grant 6,818,495 - Chiang , et al. November 16, 2 | 2004-11-16 |
Method of process simplification and eliminating topography concerns for the creation of advanced 1T-RAM devices
Grant 6,808,980 - Chen , et al. October 26, 2 | 2004-10-26 |
Methods and systems for forming embedded DRAM for an MIM capacitor
Grant 6,797,557 - Chiang September 28, 2 | 2004-09-28 |
Method of process simplification and eliminating topography concerns for the creation of advanced 1T-RAM devices
App 20040108533 - Chen, Chung-Yi ; et al. | 2004-06-10 |
MIM process for logic-based embedded RAM having front end manufacturing operation
Grant 6,656,786 - Chiang , et al. December 2, 2 | 2003-12-02 |
MIM process for logic-based embedded RAM
Grant 6,656,785 - Chiang , et al. December 2, 2 | 2003-12-02 |
Method for integrating copper process and MIM capacitor for embedded DRAM
App 20030156378 - Chiang, Min-Hsiung ; et al. | 2003-08-21 |
Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule
Grant 6,600,228 - Lee , et al. July 29, 2 | 2003-07-29 |
Novel MIM process for logic-based embedded RAM
App 20030073286 - Chiang, Min-Hsiung ; et al. | 2003-04-17 |
Compatible embedded DRAM process for MIM capacitor
App 20030073279 - Chiang, Min-Hsiung | 2003-04-17 |
Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule and device manufactured thereby
App 20020004310 - Lee, Yu-Hua ; et al. | 2002-01-10 |
Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure
Grant 6,274,426 - Lee , et al. August 14, 2 | 2001-08-14 |
Well-controlled CMP process for DRAM technology
Grant 6,159,786 - Chiang , et al. December 12, 2 | 2000-12-12 |
Method of reducing nitride and oxide peeling after planarization using an anneal
Grant 6,025,279 - Chiang , et al. February 15, 2 | 2000-02-15 |
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