Chiang, Chen Min
Patent Applications and Registrations
Patent applications and USPTO patent grants for Chiang, Chen Min.The latest application filed is for "expanding architecture for error correction code and method for the same".
- Chiang, Chen Min - Hsinchu TW
- Chiang, Chen Min - Chuiung TW
| Patent | Date |
|---|---|
| Expanding architecture for error correction code and method for the same App 20050289430 - Chen, Bryan Chih-Chen ; et al. | 2005-12-29 |
| Data reading structure App 20050283581 - Chiang, Chen Min | 2005-12-22 |
| High-speed transmission apparatus App 20050271126 - Chiang, Chen-Min ; et al. | 2005-12-08 |
| Memory circuit App 20050273532 - Chiang, Chen Min ; et al. | 2005-12-08 |
| Method and apparatus for universal serial bus (USB) physical layer App 20050235089 - Cheng, Fred ; et al. | 2005-10-20 |
| Buffer controller between memories and method for the same App 20050223126 - Chu, Li Wei ; et al. | 2005-10-06 |
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