| Patent | Date |
|---|
Trench gate structure and method of forming a trench gate structure
Grant 11,456,367 - Chi , et al. September 27, 2 | 2022-09-27 |
New Ald Method With Multi-chambers For Sic Or Multi-elements Epitaxial Growth
App 20220243359 - MENG; Zhaosheng ; et al. | 2022-08-04 |
New Method To Form Contacts With Multiple Depth By Enhanced Cesl
App 20220246470 - CHI; Min-Hwa ; et al. | 2022-08-04 |
Liner And Barrier Layer In Dual Damascene Cu Interconnect For Enhanced Em And Process
App 20220216101 - MENG; Zhaosheng ; et al. | 2022-07-07 |
Structure And Method Of New Power Mos And Igbt With Built-in Multiple Vt's
App 20220209005 - CHI; Min-Hwa ; et al. | 2022-06-30 |
Multi-bits Storage In Power Mos (and Igbt) And Simultaneous Read Methods
App 20220208765 - CHI; Min-Hwa ; et al. | 2022-06-30 |
Sige Hbt With Grenphene Extrinsic Base And Methods
App 20220208756 - CHI; Min-Hwa ; et al. | 2022-06-30 |
LDMOS transistor having vertical floating field plate and manufacture fhereof
App 20220102551 - CHI; Min-Hwa ; et al. | 2022-03-31 |
Heterojunction Bipolar Transistor And Method Of Making The Same
App 20220093774 - CHI; Min-Hwa ; et al. | 2022-03-24 |
Ldmos Transistor And Manufacture Thereof
App 20210399129 - LI; Min ; et al. | 2021-12-23 |
High Pressure Device Of Resurf Containing Ferroelectric Material And Method Of Making The Same
App 20210399086 - CHI; Min-Hwa ; et al. | 2021-12-23 |
Super Junction Power Device And Method Of Making The Same
App 20210391419 - CHI; Min-Hwa ; et al. | 2021-12-16 |
Super Junction Power Device And Method Of Making The Same
App 20210391416 - CHI; Min-Hwa ; et al. | 2021-12-16 |
Igbt Device With Narrow Mesa And Manufacture Thereof
App 20210391453 - CHI; Min-Hwa ; et al. | 2021-12-16 |
Super Junction Power Device And Method Of Making The Same
App 20210391417 - CHI; Min-Hwa ; et al. | 2021-12-16 |
Super Junction Power Device And Method Of Making The Same
App 20210391418 - CHI; Min-Hwa ; et al. | 2021-12-16 |
Trench Gate Structure And Method Of Forming A Trench Gate Structure
App 20210343850 - CHI; Min-Hwa ; et al. | 2021-11-04 |
Semiconductor device with recessed source/drain contacts and a gate contact positioned above the active region
Grant 11,011,604 - Zang , et al. May 18, 2 | 2021-05-18 |
FinFET with multilayer fins for multi-value logic (MVL) applications
Grant 10,756,213 - Chi , et al. A | 2020-08-25 |
Method, apparatus and system for improved performance using tall fins in finFET devices
Grant 10,622,463 - Zang , et al. | 2020-04-14 |
Structures of bottom select transistor for embedding 3D-NAND in BEOL and methods
Grant 10,572,380 - Li , et al. Feb | 2020-02-25 |
Non-volatile Memory And Fabrication Method Thereof
App 20200006654 - CHI; Min-Hwa ; et al. | 2020-01-02 |
Flash memory device and manufacture thereof
Grant 10,483,283 - Li , et al. Nov | 2019-11-19 |
Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby
Grant 10,475,899 - Xie , et al. Nov | 2019-11-12 |
Finfet With Multilayer Fins For Multi-value Logic (mvl) Applications And Method Of Forming
App 20190326436 - CHI; Min-hwa ; et al. | 2019-10-24 |
Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods
Grant 10,438,955 - Zang , et al. O | 2019-10-08 |
Semiconductor Device With Recessed Source/drain Contacts And A Gate Contact Positioned Above The Active Region
App 20190296108 - Zang; Hui ; et al. | 2019-09-26 |
Semiconductor device with recessed source/drain contacts and a gate contact positioned above the active region
Grant 10,396,155 - Zang , et al. A | 2019-08-27 |
FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming
Grant 10,388,790 - Chi , et al. A | 2019-08-20 |
Flash Memory Device And Manufacture Thereof
App 20190237478 - LI; Shan Rong ; et al. | 2019-08-01 |
Fin structures and multi-Vt scheme based on tapered fin and method to form
Grant 10,347,740 - Wu , et al. July 9, 2 | 2019-07-09 |
Semiconductor fuses with nanowire fuse links and fabrication methods thereof
Grant 10,332,834 - Wong , et al. | 2019-06-25 |
Flash memory device and manufacture thereof
Grant 10,297,609 - Li , et al. | 2019-05-21 |
Multiple threshold voltages using fin pitch and profile
Grant 10,290,634 - Peng , et al. | 2019-05-14 |
Circuit structures with vertically spaced transistors and fabrication methods
Grant 10,290,654 - Zang , et al. | 2019-05-14 |
Method and apparatus for reducing threshold voltage mismatch in an integrated circuit
Grant 10,276,390 - Chi , et al. | 2019-04-30 |
Method Of Forming Gate-all-around (gaa) Finfet And Gaa Finfet Formed Thereby
App 20190123160 - Xie; Ruilong ; et al. | 2019-04-25 |
Selective SAC capping on fin field effect transistor structures and related methods
Grant 10,269,811 - Chi , et al. | 2019-04-23 |
Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins
Grant 10,243,059 - Samavedan , et al. | 2019-03-26 |
Semiconductor Device With Recessed Source/drain Contacts And A Gate Contact Positioned Above The Active Region
App 20190088742 - Zang; Hui ; et al. | 2019-03-21 |
Transistor structures and fabrication methods thereof
Grant 10,204,991 - Wu , et al. Feb | 2019-02-12 |
Method, Apparatus And System For Improved Performance Using Tall Fins In Finfet Devices
App 20190043965 - Zang; Hui ; et al. | 2019-02-07 |
Transistor structure having multiple n-type and/or p-type elongated regions intersecting under common gate
Grant 10,177,157 - Zang , et al. J | 2019-01-08 |
Semiconductor device having local buried oxide
Grant 10,170,315 - Liu , et al. J | 2019-01-01 |
Devices and methods for dynamically tunable biasing to backplates and wells
Grant 10,170,353 - Zang , et al. J | 2019-01-01 |
Memory cell with recessed source/drain contacts to reduce capacitance
Grant 10,170,377 - Zang , et al. J | 2019-01-01 |
Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby
Grant 10,164,041 - Xie , et al. Dec | 2018-12-25 |
Selective Sac Capping On Fin Field Effect Transistor Structures And Related Methods
App 20180366470 - Chi; Min-hwa ; et al. | 2018-12-20 |
FINFET circuit structures with vertically spaced transistors and fabrication methods
Grant 10,147,802 - Zang , et al. De | 2018-12-04 |
OTPROM for post-process programming using selective breakdown
Grant 10,147,496 - Gautam , et al. De | 2018-12-04 |
FinFET with isolated source and drain
Grant 10,128,333 - Wong , et al. November 13, 2 | 2018-11-13 |
Integrated circuit structure without gate contact and method of forming same
Grant 10,121,893 - Zang , et al. November 6, 2 | 2018-11-06 |
Method, apparatus and system for improved performance using tall fins in finFET devices
Grant 10,115,807 - Zang , et al. October 30, 2 | 2018-10-30 |
Self-aligned back-plane and well contacts for fully depleted silicon on insulator device
Grant 10,115,738 - Zang , et al. October 30, 2 | 2018-10-30 |
Selective SAC capping on fin field effect transistor structures and related methods
Grant 10,096,604 - Chi , et al. October 9, 2 | 2018-10-09 |
Devices With Contact-to-gate Shorting Through Conductive Paths Between Fins And Fabrication Methods
App 20180286873 - ZANG; Hui ; et al. | 2018-10-04 |
Source/drain Parasitic Capacitance Reduction In Finfet-based Semiconductor Structure Having Tucked Fins
App 20180277655 - SAMAVEDAN; Srikanth Balaji ; et al. | 2018-09-27 |
Oxidizing and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines
Grant 10,068,766 - Zang , et al. September 4, 2 | 2018-09-04 |
Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins
Grant 10,056,468 - Samavedan , et al. August 21, 2 | 2018-08-21 |
Programmable via devices with metal/semiconductor via links and fabrication methods thereof
Grant 10,056,331 - Jacob , et al. August 21, 2 | 2018-08-21 |
Three-dimensional finFET transistor with portion(s) of the fin channel removed in gate-last flow
Grant 10,038,096 - Zang , et al. July 31, 2 | 2018-07-31 |
FinFET devices having asymmetrical epitaxially-grown source and drain regions and methods of forming the same
Grant 10,032,910 - Wu , et al. July 24, 2 | 2018-07-24 |
Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods
Grant 10,014,303 - Zang , et al. July 3, 2 | 2018-07-03 |
Modified tunneling field effect transistors and fabrication methods
Grant 10,003,302 - Liu , et al. June 19, 2 | 2018-06-19 |
Gate Structures With Low Resistance
App 20180158821 - XIAO; Changyong ; et al. | 2018-06-07 |
Novel Otprom For Post-process Programming Using Selective Breakdown
App 20180151238 - Gautam; Akhilesh ; et al. | 2018-05-31 |
Semiconductor fin loop for use with diffusion break
Grant 9,984,932 - Zang , et al. May 29, 2 | 2018-05-29 |
Self-aligned Back-plane And Well Contacts For Fully Depleted Silicon On Insulator Device
App 20180138203 - ZANG; Hui ; et al. | 2018-05-17 |
Semiconductor Fin Loop For Use With Diffusion Break
App 20180130711 - Zang; Hui ; et al. | 2018-05-10 |
Methods for crossed-fins FinFET device for sensing and measuring magnetic fields
Grant 9,964,605 - Chi , et al. May 8, 2 | 2018-05-08 |
Flash Memory Device And Manufacture Thereof
App 20180122823 - LI; Shan Rong ; et al. | 2018-05-03 |
Structures Of Bottom Select Transistor For Embedding 3d-nand In Beol And Methods
App 20180121345 - LI; SHAN RONG ; et al. | 2018-05-03 |
OTPROM for post-process programming using selective breakdown
Grant 9,916,903 - Gautam , et al. March 13, 2 | 2018-03-13 |
Source/drain Parasitic Capacitance Reduction In Finfet-based Semiconductor Structure Having Tucked Fins
App 20180069092 - SAMAVEDAN; Srikanth Balaji ; et al. | 2018-03-08 |
Selective Sac Capping On Fin Field Effect Transistor Structures And Related Methods
App 20180069009 - Chi; Min-hwa ; et al. | 2018-03-08 |
Integrated Circuit Structure Without Gate Contact And Method Of Forming Same
App 20180061976 - Zang; Hui ; et al. | 2018-03-01 |
Devices With Contact-to-gate Shorting Through Conductive Paths Between Fins And Fabrication Methods
App 20180061842 - ZANG; Hui ; et al. | 2018-03-01 |
Stress memorization and defect suppression techniques for NMOS transistor devices
Grant 9,905,673 - Peng , et al. February 27, 2 | 2018-02-27 |
Transistor Structure Having N-type And P-type Elongated Regions Intersecting Under Common Gate
App 20180047734 - ZANG; Hui ; et al. | 2018-02-15 |
Programmable Via Devices With Metal/semiconductor Via Links And Fabrication Methods Thereof
App 20180033726 - JACOB; Ajey P. ; et al. | 2018-02-01 |
Capacitor structures with embedded electrodes and fabrication methods thereof
Grant 9,881,738 - Zang , et al. January 30, 2 | 2018-01-30 |
Transistor structure having N-type and P-type elongated regions intersecting under common gate
Grant 9,865,603 - Zang , et al. January 9, 2 | 2018-01-09 |
Methods For Crossed-fins Finfet Device For Sensing And Measuring Magnetic Fields
App 20170371002 - CHI; Min-hwa ; et al. | 2017-12-28 |
Diodes And Fabrication Methods Thereof
App 20170365721 - CHI; Min-hwa | 2017-12-21 |
Integrated circuit structure without gate contact and method of forming same
Grant 9,842,927 - Zang , et al. December 12, 2 | 2017-12-12 |
Method, apparatus, and system for E-fuse in advanced CMOS technologies
Grant 9,831,175 - Patil , et al. November 28, 2 | 2017-11-28 |
Embedded DRAM cells having capacitors within trench silicide trenches of a semiconductor structure
Grant 9,831,248 - Zang , et al. November 28, 2 | 2017-11-28 |
FinFETs with air-gap spacers and methods for forming the same
Grant 9,831,346 - Zang , et al. November 28, 2 | 2017-11-28 |
Circuit Structures With Vertically Spaced Transistors And Fabrication Methods
App 20170338247 - ZANG; Hui ; et al. | 2017-11-23 |
Apparatus And Method Of Adjusting Work-function Metal Thickness To Provide Variable Threshold Voltages In Finfets
App 20170338156 - ZANG; Hui ; et al. | 2017-11-23 |
Finfet Circuit Structures With Vertically Spaced Transistors And Fabrication Methods
App 20170338235 - ZANG; Hui ; et al. | 2017-11-23 |
SRAM bitcell structures facilitating biasing of pull-up transistors
Grant 9,824,748 - Zang , et al. November 21, 2 | 2017-11-21 |
Metal-insulator-metal capacitor and methods of fabrication
Grant 9,818,689 - Zang , et al. November 14, 2 | 2017-11-14 |
Programmable via devices with metal/semiconductor via links and fabrication methods thereof
Grant 9,812,393 - Jacob , et al. November 7, 2 | 2017-11-07 |
Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETs
Grant 9,805,982 - Zang , et al. October 31, 2 | 2017-10-31 |
Metal-insulator-metal Capacitor And Methods Of Fabrication
App 20170309563 - ZANG; Hui ; et al. | 2017-10-26 |
SRAM bitcell structures facilitating biasing of pull-down transistors
Grant 9,799,661 - Zang , et al. October 24, 2 | 2017-10-24 |
Protecting, oxidizing, and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines
Grant 9,799,514 - Zang , et al. October 24, 2 | 2017-10-24 |
Method And Apparatus For Reducing Threshold Voltage Mismatch In An Integrated Circuit
App 20170301544 - CHI; Min-hwa ; et al. | 2017-10-19 |
Devices And Methods For Dynamically Tunable Biasing To Backplates And Wells
App 20170294336 - ZANG; Hui ; et al. | 2017-10-12 |
Protecting, Oxidizing, And Etching Of Material Lines For Use In Increasing Or Decreasing Critical Dimensions Of Hard Mask Lines
App 20170294308 - ZANG; Hui ; et al. | 2017-10-12 |
Oxidizing And Etching Of Material Lines For Use In Increasing Or Decreasing Critical Dimensions Of Hard Mask Lines
App 20170294309 - ZANG; Hui ; et al. | 2017-10-12 |
Finfet With Isolated Source And Drain
App 20170288016 - WONG; Hoong Shing ; et al. | 2017-10-05 |
Stress Memorization And Defect Suppression Techniques For Nmos Transistor Devices
App 20170278949 - PENG; Wen-Pin ; et al. | 2017-09-28 |
Diodes and fabrication methods thereof
Grant 9,768,325 - Chi September 19, 2 | 2017-09-19 |
Integrated circuits including replacement gate structures and methods for fabricating the same
Grant 9,761,691 - Shin , et al. September 12, 2 | 2017-09-12 |
Semiconductor structure with anti-efuse device
Grant 9,754,903 - Patil , et al. September 5, 2 | 2017-09-05 |
Contacts for a fin-type field-effect transistor
Grant 9,741,615 - Zang , et al. August 22, 2 | 2017-08-22 |
SRAM bitcell structures facilitating biasing of pass gate transistors
Grant 9,734,897 - Zang , et al. August 15, 2 | 2017-08-15 |
Fabricating field effect transistor(s) with stressed channel region(s) and low-resistance source/drain regions
Grant 9,735,057 - Shintri , et al. August 15, 2 | 2017-08-15 |
Modified Tunneling Field Effect Transistors And Fabrication Methods
App 20170230004 - LIU; Yanxiang ; et al. | 2017-08-10 |
Method, Apparatus, And System For E-fuse In Advanced Cmos Technologies
App 20170221823 - Patil; Suraj Kumar ; et al. | 2017-08-03 |
Transistor Structures And Fabrication Methods Thereof
App 20170213890 - WU; Xusheng ; et al. | 2017-07-27 |
Devices and methods for dynamically tunable biasing to backplates and wells
Grant 9,716,138 - Zang , et al. July 25, 2 | 2017-07-25 |
Multiple Threshold Voltages Using Fin Pitch And Profile
App 20170207216 - PENG; Wen Pin ; et al. | 2017-07-20 |
Stress Memorization And Defect Suppression Techniques For Nmos Transistor Devices
App 20170207090 - PENG; Wen-Pin ; et al. | 2017-07-20 |
Self-aligned Source/drain Contact In Replacement Metal Gate Process
App 20170207118 - PENG; Wen Pin ; et al. | 2017-07-20 |
Stress memorization and defect suppression techniques for NMOS transistor devices
Grant 9,711,619 - Peng , et al. July 18, 2 | 2017-07-18 |
Fabrication Of Transistor-based Semiconductor Device Using Closed-loop Fins
App 20170200786 - ZANG; Hui ; et al. | 2017-07-13 |
Methods of forming CMOS based integrated circuit products using disposable spacers
Grant 9,704,759 - Peng , et al. July 11, 2 | 2017-07-11 |
Integrated circuits with replacement metal gates and methods for fabricating the same
Grant 9,698,241 - Patil , et al. July 4, 2 | 2017-07-04 |
Conformal nitridation of one or more fin-type transistor layers
Grant 9,698,269 - Tong , et al. July 4, 2 | 2017-07-04 |
Programmable devices with current-facilitated migration and fabrication methods
Grant 9,691,497 - Patil , et al. June 27, 2 | 2017-06-27 |
Modified tunneling field effect transistors and fabrication methods
Grant 9,673,757 - Liu , et al. June 6, 2 | 2017-06-06 |
Method, apparatus, and system for e-fuse in advanced CMOS technologies
Grant 9,659,862 - Patil , et al. May 23, 2 | 2017-05-23 |
Semiconductor Fuses With Nanowire Fuse Links And Fabrication Methods Thereof
App 20170141031 - WONG; Chun Yu ; et al. | 2017-05-18 |
Method, Apparatus And System For Improved Performance Using Tall Fins In Finfet Devices
App 20170141214 - Zang; Hui ; et al. | 2017-05-18 |
Methods of forming diffusion breaks on integrated circuit products comprised of finFET devices
Grant 9,653,583 - Zhao , et al. May 16, 2 | 2017-05-16 |
Method, Apparatus, And System For E-fuse In Advanced Cmos Technologies
App 20170133319 - Patil; Suraj Kumar ; et al. | 2017-05-11 |
Transistor structures and fabrication methods thereof
Grant 9,647,073 - Wu , et al. May 9, 2 | 2017-05-09 |
Semiconductor Structure With Anti-efuse Device
App 20170125361 - PATIL; Suraj K. ; et al. | 2017-05-04 |
Method of adjusting spacer thickness to provide variable threshold voltages in FinFETs
Grant 9,620,425 - Zang , et al. April 11, 2 | 2017-04-11 |
Programmable Devices With Current-facilitated Migration And Fabrication Methods
App 20170092373 - PATIL; Suraj K. ; et al. | 2017-03-30 |
Programmable Via Devices With Metal/semiconductor Via Links And Fabrication Methods Thereof
App 20170092583 - JACOB; Ajey P. ; et al. | 2017-03-30 |
Fin Structures And Multi-vt Scheme Based On Tapered Fin And Method To Form
App 20170084718 - WU; Xusheng ; et al. | 2017-03-23 |
Semiconductor fuses with nanowire fuse links and fabrication methods thereof
Grant 9,601,428 - Wong , et al. March 21, 2 | 2017-03-21 |
Three-dimensional semiconductor device with co-fabricated adjacent capacitor
Grant 9,601,495 - Zang , et al. March 21, 2 | 2017-03-21 |
Three-dimensional Finfet Transistor With Portion(s) Of The Fin Channel Removed In Gate-last Flow
App 20170069759 - ZANG; Hui ; et al. | 2017-03-09 |
Methods Of Forming Cmos Based Integrated Circuit Products Using Disposable Spacers
App 20170069547 - Peng; Wen Pin ; et al. | 2017-03-09 |
Methods For Fabricating Programmable Devices And Related Structures
App 20170062442 - PATIL; Suraj K. ; et al. | 2017-03-02 |
Fin structures and multi-Vt scheme based on tapered fin and method to form
Grant 9,583,625 - Wu , et al. February 28, 2 | 2017-02-28 |
Semiconductor charge pump with imbedded capacitor
Grant 9,583,479 - Zang , et al. February 28, 2 | 2017-02-28 |
Bipolar transistor, band-gap reference circuit and virtual ground reference circuit and methods of fabricating thereof
Grant 9,577,063 - Chi , et al. February 21, 2 | 2017-02-21 |
Multiple layer interface formation for semiconductor structure
Grant 9,570,572 - Patil , et al. February 14, 2 | 2017-02-14 |
Capacitor Structures With Embedded Electrodes And Fabrication Methods Thereof
App 20170040110 - ZANG; Hui ; et al. | 2017-02-09 |
Methods for fabricating programmable devices and related structures
Grant 9,564,447 - Patil , et al. February 7, 2 | 2017-02-07 |
Three-dimensional Semiconductor Device With Co-fabricated Adjacent Capacitor
App 20170033113 - ZANG; Hui ; et al. | 2017-02-02 |
Fabricating transistors having resurfaced source/drain regions with stressed portions
Grant 9,559,166 - Ray , et al. January 31, 2 | 2017-01-31 |
Connecting to back-plate contacts or diode junctions through a RMG electrode and resulting devices
Grant 9,548,318 - Chi , et al. January 17, 2 | 2017-01-17 |
Shallow trench isolation structure with sigma cavity
Grant 9,548,357 - Tsai , et al. January 17, 2 | 2017-01-17 |
Single diffusion break structure and cuts later method of making
Grant 9,543,298 - Zang , et al. January 10, 2 | 2017-01-10 |
Single diffusion break structure
Grant 9,536,991 - Zang , et al. January 3, 2 | 2017-01-03 |
Method for creating self-aligned SDB for minimum gate-junction pitch and epitaxy formation in a fin-type IC device
Grant 9,524,911 - Tsai , et al. December 20, 2 | 2016-12-20 |
Diodes And Fabrication Methods Thereof
App 20160359056 - CHI; Min-hwa | 2016-12-08 |
Methods of fabricating nanowire structures
Grant 9,508,795 - Wong , et al. November 29, 2 | 2016-11-29 |
Fabrication methods for multi-layer semiconductor structures
Grant 9,502,301 - Patil , et al. November 22, 2 | 2016-11-22 |
Fabricating raised fins using ancillary fin structures
Grant 9,490,174 - Wu , et al. November 8, 2 | 2016-11-08 |
Finfet Devices Having Asymmetrical Epitaxially-grown Source And Drain Regions And Methods Of Forming The Same
App 20160315172 - Wu; Xusheng ; et al. | 2016-10-27 |
Metal resistor using FinFET-based replacement gate process
Grant 9,478,625 - Zang , et al. October 25, 2 | 2016-10-25 |
Integrated device with inductive and capacitive portions and fabrication methods
Grant 9,460,996 - Zang , et al. October 4, 2 | 2016-10-04 |
Semiconductor Fuses With Nanowire Fuse Links And Fabrication Methods Thereof
App 20160284643 - WONG; Chun Yu ; et al. | 2016-09-29 |
Forming Tunneling Field-effect Transistor With Stacking Fault And Resulting Device
App 20160284846 - LIU; Yanxiang ; et al. | 2016-09-29 |
Merged N/p Type Transistor
App 20160276350 - ZANG; Hui ; et al. | 2016-09-22 |
Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology
Grant 9,443,771 - Shen , et al. September 13, 2 | 2016-09-13 |
Methods of facilitating fabricating transistors
Grant 9,425,100 - Shen , et al. August 23, 2 | 2016-08-23 |
Method for integrating thin-film transistors on an isolation region in an integrated circuit and resulting device
Grant 9,419,015 - Wu , et al. August 16, 2 | 2016-08-16 |
Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology
Grant 9,418,899 - Shen , et al. August 16, 2 | 2016-08-16 |
Method Of Multi-wf For Multi-vt And Thin Sidewall Deposition By Implantation For Gate-last Planar Cmos And Finfet Technology
App 20160225675 - SHEN; Yan Ping ; et al. | 2016-08-04 |
Fabricating Transistors Having Resurfaced Source/drain Regions With Stressed Portions
App 20160225852 - RAY; Shishir ; et al. | 2016-08-04 |
Methods Of Fabricating Nanowire Structures
App 20160225849 - WONG; Chun Yu ; et al. | 2016-08-04 |
Bipolar Transistor, Band-gap Reference Circuit And Virtual Ground Reference Circuit
App 20160218194 - CHI; MIN-HWA ; et al. | 2016-07-28 |
Finfet With Multilayer Fins For Multi-value Logic (mvl) Applications And Method Of Forming
App 20160211375 - CHI; Min-hwa ; et al. | 2016-07-21 |
MOL contact metallization scheme for improved yield and device reliability
Grant 9,396,995 - Patil , et al. July 19, 2 | 2016-07-19 |
Methods of forming reduced thickness spacers in CMOS based integrated circuit products
Grant 9,385,124 - Peng , et al. July 5, 2 | 2016-07-05 |
Silicon-on-insulator finFET with bulk source and drain
Grant 9,385,126 - Liu , et al. July 5, 2 | 2016-07-05 |
Fabrication Methods For Multi-layer Semiconductor Structures
App 20160190014 - PATIL; Suraj K. ; et al. | 2016-06-30 |
Conformal Nitridation Of One Or More Fin-type Transistor Layers
App 20160190324 - TONG; Wei Hua ; et al. | 2016-06-30 |
Fet structure for minimum size length/width devices for performance boost and mismatch reduction
Grant 9,379,186 - Wang , et al. June 28, 2 | 2016-06-28 |
Selectively forming a protective conductive cap on a metal gate electrode
Grant 9,379,209 - Cai , et al. June 28, 2 | 2016-06-28 |
Integrated Circuits Including Replacement Gate Structures And Methods For Fabricating The Same
App 20160163824 - Shin; Dong-Woon ; et al. | 2016-06-09 |
FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming
Grant 9,362,277 - Chi , et al. June 7, 2 | 2016-06-07 |
Selectively Forming A Protective Conductive Cap On A Metal Gate Electrode
App 20160133721 - Cai; Xiuyu ; et al. | 2016-05-12 |
Bipolar transistor, band-gap reference circuit and virtual ground reference circuit
Grant 9,337,324 - Chi , et al. May 10, 2 | 2016-05-10 |
FinFET with active region shaped structures and channel separation
Grant 9,337,340 - Chi , et al. May 10, 2 | 2016-05-10 |
Embedded Dram In Replacement Metal Gate Technology
App 20160126245 - LIU; Yanxiang ; et al. | 2016-05-05 |
Transistor Structures And Fabrication Methods Thereof
App 20160126316 - WU; Xusheng ; et al. | 2016-05-05 |
Method Of Improved Ca/cb Contact And Device Thereof
App 20160126336 - WU; Xusheng ; et al. | 2016-05-05 |
Fabricating transistor(s) with raised active regions having angled upper surfaces
Grant 9,331,159 - Jha , et al. May 3, 2 | 2016-05-03 |
Fin Structures And Multi-vt Scheme Based On Tapered Fin And Method To Form
App 20160118500 - WU; Xusheng ; et al. | 2016-04-28 |
Multiple Layer Interface Formation For Semiconductor Structure
App 20160118468 - PATIL; Suraj K. ; et al. | 2016-04-28 |
Fin Device With Blocking Layer In Channel Region
App 20160111491 - Jacob; Ajey P. ; et al. | 2016-04-21 |
Finfet Semiconductor Device Having Local Buried Oxide
App 20160111322 - LIU; Yanxiang ; et al. | 2016-04-21 |
Novel Otprom For Post-process Programming Using Selective Breakdown
App 20160104541 - Gautam; Akhilesh ; et al. | 2016-04-14 |
Conformal nitridation of one or more fin-type transistor layers
Grant 9,312,145 - Tong , et al. April 12, 2 | 2016-04-12 |
T-shaped contacts for semiconductor device
Grant 9,299,608 - Wu , et al. March 29, 2 | 2016-03-29 |
Fin Device With Blocking Layer In Channel Region
App 20160071979 - Jacob; Ajey P. ; et al. | 2016-03-10 |
Non-planar Esd Device For Non-planar Output Transistor And Common Fabrication Thereof
App 20160064371 - LEE; Jian-Hsing ; et al. | 2016-03-03 |
Semiconductor Gate With Wide Top Or Bottom
App 20160049488 - SHEN; Yan Ping ; et al. | 2016-02-18 |
Fin device with blocking layer in channel region
Grant 9,263,587 - Jacob , et al. February 16, 2 | 2016-02-16 |
FinFET semiconductor device having local buried oxide
Grant 9,252,272 - Liu , et al. February 2, 2 | 2016-02-02 |
Shallow Trench Isolation Structure With Sigma Cavity
App 20160020275 - Tsai; HaoCheng ; et al. | 2016-01-21 |
Devices And Methods Of Forming Bulk Finfets With Lateral Seg For Source And Drain On Dielectrics
App 20150357332 - LIU; Jin Ping ; et al. | 2015-12-10 |
Conductor layout technique to reduce stress-induced void formations
Grant 9,209,079 - Chi , et al. December 8, 2 | 2015-12-08 |
T-shaped Contacts For Semiconductor Device
App 20150332963 - WU; Xusheng ; et al. | 2015-11-19 |
Fabricating Raised Fins Using Ancillary Fin Structures
App 20150332972 - WU; Xusheng ; et al. | 2015-11-19 |
Fabricating Field Effect Transistor(s) With Stressed Channel Region(s) And Low-resistance Source/drain Regions
App 20150311120 - SHINTRI; Shashidhar Shreeshail ; et al. | 2015-10-29 |
Silicon-on-insulator Finfet With Bulk Source And Drain
App 20150287727 - Liu; Yanxiang ; et al. | 2015-10-08 |
Methods of manufacturing integrated circuits having FinFET structures with epitaxially formed source/drain regions
Grant 9,153,496 - Wong , et al. October 6, 2 | 2015-10-06 |
Embedded selector-less one-time programmable non-volatile memory
Grant 9,142,316 - Liu , et al. September 22, 2 | 2015-09-22 |
Devices and methods of forming bulk FinFETS with lateral seg for source and drain on dielectrics
Grant 9,142,673 - Liu , et al. September 22, 2 | 2015-09-22 |
Replacement Fin Insolation In A Semiconductor Device
App 20150255456 - Jacob; Ajey Poovannummoottil ; et al. | 2015-09-10 |
Conformal Nitridation Of One Or More Fin-type Transistor Layers
App 20150255277 - TONG; Wei Hua ; et al. | 2015-09-10 |
Finfet With Multilayer Fins For Multi-value Logic (mvl) Applications And Method Of Forming
App 20150228648 - CHI; Min-hwa ; et al. | 2015-08-13 |
Finfet With Isolated Source And Drain
App 20150221726 - Wong; Hoong Shing ; et al. | 2015-08-06 |
Silicon-on-insulator finFET with bulk source and drain
Grant 9,087,743 - Liu , et al. July 21, 2 | 2015-07-21 |
Mos Transistor Operated As Otp Cell With Gate Dielectric Operating As An E-fuse Element
App 20150200251 - CHI; Min-hwa ; et al. | 2015-07-16 |
Modified Tunneling Field Effect Transistors And Fabrication Methods
App 20150200298 - LIU; Yanxiang ; et al. | 2015-07-16 |
Shallow trench isolation structure with sigma cavity
Grant 9,076,868 - Tsai , et al. July 7, 2 | 2015-07-07 |
MOS transistor operated as OTP cell with gate dielectric operating as an e-fuse element
Grant 9,076,791 - Chi , et al. July 7, 2 | 2015-07-07 |
Finfet With Active Region Shaped Structures And Channel Separation
App 20150187947 - CHI; Min-Hwa ; et al. | 2015-07-02 |
Forming tunneling field-effect transistor with stacking fault and resulting device
Grant 9,064,888 - Liu , et al. June 23, 2 | 2015-06-23 |
Finfet Semiconductor Device Having Local Buried Oxide
App 20150137235 - LIU; Yanxiang ; et al. | 2015-05-21 |
Silicon-on-insulator Finfet With Bulk Source And Drain
App 20150137236 - Liu; Yanxiang ; et al. | 2015-05-21 |
Methods Of Forming Stressed Multilayer Finfet Devices With Alternative Channel Materials
App 20150126008 - Paul; Abhijeet ; et al. | 2015-05-07 |
Methods of forming stressed multilayer FinFET devices with alternative channel materials
Grant 9,023,705 - Paul , et al. May 5, 2 | 2015-05-05 |
Methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices
Grant 9,012,286 - Chi April 21, 2 | 2015-04-21 |
Combination FinFET and planar FET semiconductor device and methods of making such a device
Grant 9,012,986 - Chi , et al. April 21, 2 | 2015-04-21 |
Integrated circuits with programmable electrical connections and methods for fabricating the same
Grant 9,007,803 - Liu , et al. April 14, 2 | 2015-04-14 |
FinFET with active region shaped structures and channel separation
Grant 9,006,066 - Chi , et al. April 14, 2 | 2015-04-14 |
Methods Of Manufacturing Integrated Circuits Having Finfet Structures With Epitaxially Formed Source/drain Regions
App 20150099336 - Wong; Hoong Shing ; et al. | 2015-04-09 |
Method of fabricating a magnetic tunnel junction device
Grant 8,975,091 - Chi , et al. March 10, 2 | 2015-03-10 |
Embedded Selector-less One-time Programmable Non-volatile Memory
App 20150062996 - LIU; Yanxiang ; et al. | 2015-03-05 |
Devices And Methods Of Forming Bulk Finfets With Lateral Seg For Source And Drain On Dielectrics
App 20150035018 - LIU; Jin Ping ; et al. | 2015-02-05 |
Methods of manufacturing integrated circuits having FinFET structures with epitaxially formed source/drain regions
Grant 8,946,029 - Wong , et al. February 3, 2 | 2015-02-03 |
Semiconductor Device Having Local Buried Oxide
App 20150024557 - LIU; Yanxiang ; et al. | 2015-01-22 |
Integrated Circuits With Programmable Electrical Connections And Methods For Fabricating The Same
App 20150016174 - Liu; Yanxiang ; et al. | 2015-01-15 |
Novel Conductor Layout Technique To Reduce Stress-induced Void Formations
App 20150011086 - CHI; Min-Hwa ; et al. | 2015-01-08 |
Forming Tunneling Field-effect Transistor With Stacking Fault And Resulting Device
App 20150001594 - LIU; Yanxiang ; et al. | 2015-01-01 |
Method Of Fabricating A Magnetic Tunnel Junction Device
App 20140377884 - CHI; Min-Hwa ; et al. | 2014-12-25 |
Wrap around stressor formation
Grant 8,906,768 - Wong , et al. December 9, 2 | 2014-12-09 |
Bipolar Transistor, Band-gap Reference Circuit And Virtual Ground Reference Circuit
App 20140354347 - CHI; MIN-HWA ; et al. | 2014-12-04 |
Finfet With Active Region Shaped Structures And Channel Separation
App 20140319615 - CHI; Min-Hwa ; et al. | 2014-10-30 |
Methods Of Forming A Finfet Semiconductor Device By Performing An Epitaxial Growth Process
App 20140319624 - Chi; Min-hwa ; et al. | 2014-10-30 |
Wrap Around Stressor Formation
App 20140264489 - WONG; Hoong Shing ; et al. | 2014-09-18 |
Conductor layout technique to reduce stress-induced void formations
Grant 8,836,141 - Chi , et al. September 16, 2 | 2014-09-16 |
Combination Finfet And Planar Fet Semiconductor Device And Methods Of Making Such A Device
App 20140252480 - Chi; Min-hwa ; et al. | 2014-09-11 |
Methods of forming a FinFET semiconductor device by performing an epitaxial growth process
Grant 8,815,659 - Chi , et al. August 26, 2 | 2014-08-26 |
Combination FinFET and planar FET semiconductor device and methods of making such a device
Grant 8,772,117 - Chi , et al. July 8, 2 | 2014-07-08 |
Methods of forming self-aligned contacts for a semiconductor device formed using replacement gate techniques
Grant 8,772,102 - Chi July 8, 2 | 2014-07-08 |
Methods Of Forming A Finfet Semiconductor Device By Performing An Epitaxial Growth Process
App 20140167120 - Chi; Min-hwa ; et al. | 2014-06-19 |
Combination Finfet And Planar Fet Semiconductor Device And Methods Of Making Such A Device
App 20140151807 - Chi; Min-hwa ; et al. | 2014-06-05 |
Methods of forming self-aligned contacts for a semiconductor device
Grant 8,741,723 - Chi June 3, 2 | 2014-06-03 |
Integrated Circuits And Methods For Fabricating Integrated Circuits With Salicide Contacts On Non-planar Source/drain Regions
App 20140131777 - Wong; Hoong Shing ; et al. | 2014-05-15 |
Methods Of Manufacturing Integrated Circuits Having Finfet Structures With Epitaxially Formed Source/drain Regions
App 20140134814 - Wong; Hoong Shing ; et al. | 2014-05-15 |
Logic switch and circuits utilizing the switch
Grant 8,685,812 - Chi April 1, 2 | 2014-04-01 |
Methods of forming fins and isolation regions on a FinFET semiconductor device
Grant 8,674,413 - Chi March 18, 2 | 2014-03-18 |
Fin removal method
Grant 08617996 - | 2013-12-31 |
Fin removal method
Grant 8,617,996 - Chi , et al. December 31, 2 | 2013-12-31 |
Magnetic tunnel junction device and its fabricating method
Grant 8,574,927 - Chi , et al. November 5, 2 | 2013-11-05 |
Methods Of Forming Self-aligned Contacts For A Semiconductor Device
App 20130288471 - Chi; Min-Hwa | 2013-10-31 |
Methods Of Forming Self-aligned Contacts For A Semiconductor Device Formed Using Replacement Gate Techniques
App 20130288468 - Chi; Min-Hwa | 2013-10-31 |
Methods Of Forming Finfet Semiconductor Devices So As To Tune The Threshold Voltage Of Such Devices
App 20130270641 - Chi; Min-Hwa | 2013-10-17 |
Novel Conductor Layout Technique To Reduce Stress-induced Void Formations
App 20130241079 - Chi; Min-Hwa ; et al. | 2013-09-19 |
Multi-level flash memory cell capable of fast programming
Grant 8,466,505 - Lai , et al. June 18, 2 | 2013-06-18 |
Logic Switch and Circuits Utilizing the Switch
App 20130143370 - Chi; Min-Hwa | 2013-06-06 |
Resistive random access memory and the method of operating the same
Grant 8,451,646 - Chi , et al. May 28, 2 | 2013-05-28 |
Conductor layout technique to reduce stress-induced void formations
Grant 8,435,802 - Chi , et al. May 7, 2 | 2013-05-07 |
Novel Magnetic Tunnel Junction Device And Its Fabricating Method
App 20130099335 - Chi; Min-Hwa ; et al. | 2013-04-25 |
Semiconductor device and fabrication thereof
Grant 8,421,166 - Chi , et al. April 16, 2 | 2013-04-16 |
Logic switch and circuits utilizing the switch
Grant 8,362,528 - Chi January 29, 2 | 2013-01-29 |
Atomic layer deposition method and semiconductor device formed by the same
Grant 8,273,639 - Ji , et al. September 25, 2 | 2012-09-25 |
Green transistor for nano-Si ferro-electric RAM and method of operating the same
Grant 8,264,863 - Chi , et al. September 11, 2 | 2012-09-11 |
Semiconductor Non-volatile Memory Device
App 20120168853 - Ji; Hua ; et al. | 2012-07-05 |
Green transistor for resistive random access memory and method of operating the same
Grant 8,208,286 - Chi , et al. June 26, 2 | 2012-06-26 |
Atomic layer deposition method and semiconductor device formed by the same
Grant 8,158,512 - Ji , et al. April 17, 2 | 2012-04-17 |
Semiconductor Device And Fabrication Thereof
App 20110260220 - CHI; Min-Hwa ; et al. | 2011-10-27 |
Semiconductor device and fabrication thereof
Grant 7,994,040 - Chi , et al. August 9, 2 | 2011-08-09 |
Green Transistor For Nano-si Ferro-electric Ram And Method Of Operating The Same
App 20110090731 - Chi; Min-hwa ; et al. | 2011-04-21 |
Green Transistor for Resistive Random Access Memory and Method of Operating the Same
App 20110063888 - Chi; Min-hwa ; et al. | 2011-03-17 |
Resistive Random Access Memory and the Method of Operating the Same
App 20110051496 - CHI; Min-hwa ; et al. | 2011-03-03 |
Bipolar Transistor, Band-Gap Reference Circuit and Virtual Ground Reference Circuit
App 20110018608 - Chi; Min-hwa ; et al. | 2011-01-27 |
Vertical resistors
Grant 7,804,155 - Chi September 28, 2 | 2010-09-28 |
Hybrid Schottky source-drain CMOS for high mobility and low barrier
Grant 7,737,532 - Ke , et al. June 15, 2 | 2010-06-15 |
Atomic layer deposition method and semiconductor device formed by the same
Grant 7,709,386 - Ji , et al. May 4, 2 | 2010-05-04 |
Logic Switch and Circuits Utilizing the Switch
App 20100044795 - Chi; Min-Hwa | 2010-02-25 |
Logic switch and circuits utilizing the switch
Grant 7,635,882 - Chi December 22, 2 | 2009-12-22 |
Memory cell
Grant 7,633,110 - Chi , et al. December 15, 2 | 2009-12-15 |
SONOS type two-bit FinFET flash memory cell
Grant 7,589,387 - Hwang , et al. September 15, 2 | 2009-09-15 |
Quasi-plannar and FinFET-like transistors on bulk silicon
Grant 7,564,105 - Chi , et al. July 21, 2 | 2009-07-21 |
Vertical Resistors And Band-gap Voltage Reference Circuits
App 20090160024 - Chi; Min-Hwa | 2009-06-25 |
Vertical resistors and band-gap voltage reference circuits
Grant 7,498,657 - Chi March 3, 2 | 2009-03-03 |
Atomic Layer Deposition Method and Semiconductor Device Formed by the Same
App 20080315292 - Ji; Hua ; et al. | 2008-12-25 |
Atomic Layer Deposition Method and Semiconductor Device Formed by the Same
App 20080315295 - Ji; Hua ; et al. | 2008-12-25 |
Atomic Layer Deposition Method and Semiconductor Device Formed by the Same
App 20080315293 - Ji; Hua ; et al. | 2008-12-25 |
Semiconductor device and fabrication thereof
App 20080254579 - Chi; Min-Hwa ; et al. | 2008-10-16 |
Embedded Semiconductor Memory Devices And Methods For Fabricating The Same
App 20080145985 - CHI; Min-hwa | 2008-06-19 |
Amorphous carbon contact film for contact hole etch process
Grant 7,371,634 - Chiang , et al. May 13, 2 | 2008-05-13 |
Shallow trench filled with two or more dielectrics for isolation and coupling for stress control
Grant 7,320,926 - Chi January 22, 2 | 2008-01-22 |
Novel conductor layout technique to reduce stress-induced void formations
App 20070269907 - Chi; Min-Hwa ; et al. | 2007-11-22 |
Method for forming dual damascene with improved etch profiles
Grant 7,291,553 - Chen , et al. November 6, 2 | 2007-11-06 |
SONOS type two-bit FinFET flash memory cell
App 20070076477 - Hwang; Jiunn-Ren ; et al. | 2007-04-05 |
Hybrid Schottky source-drain CMOS for high mobility and low barrier
App 20070052027 - Ke; Chung-Hu ; et al. | 2007-03-08 |
Multi-purpose semiconductor device
App 20070045719 - Wang; Chih-Hao ; et al. | 2007-03-01 |
High performance CMOS with metal-gate and Schottky source/drain
Grant 7,176,537 - Lee , et al. February 13, 2 | 2007-02-13 |
High performance CMOS with metal-gate and Schottky source/drain
App 20060273409 - Lee; Wen-Chin ; et al. | 2006-12-07 |
Method of forming polysilicon gate structures with specific edge profiles for optimization of LDD offset spacing
Grant 7,129,140 - Chen , et al. October 31, 2 | 2006-10-31 |
Method for forming dual damascene with improved etch profiles
App 20060205207 - Chen; Cheng-Ku ; et al. | 2006-09-14 |
Multi-level flash memory cell capable of fast programming
App 20060202254 - Lai; Li-Shyue ; et al. | 2006-09-14 |
Method of predicting high-k semiconductor device lifetime
Grant 7,106,088 - Tsai , et al. September 12, 2 | 2006-09-12 |
Amorphous carbon contact film for contact hole etch process
App 20060170058 - Chiang; Wen-Chuan ; et al. | 2006-08-03 |
Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials
Grant 7,081,395 - Chi , et al. July 25, 2 | 2006-07-25 |
Method Of Predicting High-k Semiconductor Device Lifetime
App 20060158210 - Tsai; Ching-Wei ; et al. | 2006-07-20 |
Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents
Grant 7,078,766 - Chi July 18, 2 | 2006-07-18 |
Capacitor-less 1T-DRAM cell with Schottky source and drain
App 20060125121 - Ko; Chih-Hsin ; et al. | 2006-06-15 |
Shallow trench filled with two or more dielectrics for isolation and coupling for stress control
App 20060121394 - Chi; Min-Hwa | 2006-06-08 |
Self-aligned gated p-i-n diode for ultra-fast switching
App 20060091490 - Chen; Hung-Wei ; et al. | 2006-05-04 |
Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control
Grant 7,018,886 - Chi March 28, 2 | 2006-03-28 |
Memory cell
App 20060060909 - Chi; Min-Hwa ; et al. | 2006-03-23 |
Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents
Grant 7,002,213 - Chi February 21, 2 | 2006-02-21 |
Logic switch and circuits utilizing the switch
App 20060033128 - Chi; Min-Hwa | 2006-02-16 |
Quasi-plannar and FinFET-like transistors on bulk silicon
App 20050239254 - Chi, Min-Hwa ; et al. | 2005-10-27 |
Vertical resistors and band-gap voltage reference circuits
App 20050212083 - Chi, Min-Hwa | 2005-09-29 |
Method for fabricating poly patterns
Grant 6,949,471 - Hao , et al. September 27, 2 | 2005-09-27 |
Method of forming polysilicon gate structures with specific edge profiles for optimization of LDD offset spacing
App 20050202642 - Chen, Cheng-Ku ; et al. | 2005-09-15 |
Modification of carrier mobility in a semiconductor device
Grant 6,943,391 - Chi , et al. September 13, 2 | 2005-09-13 |
Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents
App 20050184340 - Chi, Min-hwa | 2005-08-25 |
Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process
Grant 6,905,929 - Merrill , et al. June 14, 2 | 2005-06-14 |
Modification of carrier mobility in a semiconductor device
App 20050110039 - Chi, Min-Hwa ; et al. | 2005-05-26 |
Storage element and SRAM cell structures using vertical FETs controlled by adjacent junction bias through shallow trench isolation
Grant 6,885,068 - Chi April 26, 2 | 2005-04-26 |
Gate-controlled, negative resistance diode device using band-to-band tunneling
Grant 6,855,587 - Chi February 15, 2 | 2005-02-15 |
Method for fabricating poly patterns
App 20050026406 - Hao, Ching-Chen ; et al. | 2005-02-03 |
Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control
Grant 6,828,211 - Chi December 7, 2 | 2004-12-07 |
Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials
App 20040232513 - Chi, Min-Hwa ; et al. | 2004-11-25 |
Low temperature MIM capacitor for mixed-signal/RF applications
Grant 6,822,283 - Lin , et al. November 23, 2 | 2004-11-23 |
Storage element and SRAM cell structures using vertical FETs controlled by adjacent junction bias through shallow trench isolation
App 20040214384 - Chi, Min-Hwa | 2004-10-28 |
Storage element and SRAM cell structures using vertical FETS controlled by adjacent junction bias through shallow trench isolation
Grant 6,759,699 - Chi July 6, 2 | 2004-07-06 |
Gate-controlled, negative resistance diode device using band-to-band tunneling
App 20040084689 - Chi, Min-Hwa | 2004-05-06 |
Structures of vertical resistors and FETs as controlled by electrical field penetration and a band-gap voltage reference using vertical FETs operating in accumulation through the field penetration effect
App 20040070050 - Chi, Min Hwa | 2004-04-15 |
Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control
App 20040063300 - Chi, Min-Hwa | 2004-04-01 |
Low temperature MIM capacitor for mixed-signal/RF applications
App 20040009646 - Lin, Dahcheng ; et al. | 2004-01-15 |
Method of forming shallow trench isolation with rounded corners and divot-free by using in-situ formed spacers
Grant 6,670,279 - Pai , et al. December 30, 2 | 2003-12-30 |
Gate-controlled, negative resistance diode device using band-to-band tunneling
Grant 6,657,240 - Chi December 2, 2 | 2003-12-02 |
CMOS transistor on thin silicon-on-insulator using accumulation as conduction mechanism
App 20030203544 - Chi, Min-Hwa | 2003-10-30 |
Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer
Grant 6,555,442 - Pai , et al. April 29, 2 | 2003-04-29 |
Fabrication methods of vertical metal-insulator-metal (MIM) capacitor for advanced embedded DRAM applications
Grant 6,528,366 - Tu , et al. March 4, 2 | 2003-03-04 |
Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM
Grant 6,500,706 - Chi December 31, 2 | 2002-12-31 |
Capacitor under bitline (CUB) memory cell structure employing air gap void isolation
Grant 6,501,120 - Tu , et al. December 31, 2 | 2002-12-31 |
Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications
Grant 6,486,529 - Chi , et al. November 26, 2 | 2002-11-26 |
Methods for forming memory cell structures
Grant 6,486,025 - Liu , et al. November 26, 2 | 2002-11-26 |
Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications
App 20020123159 - Chi, Min-Hwa ; et al. | 2002-09-05 |
Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents
App 20020074599 - Chi, Min-hwa | 2002-06-20 |
Scheme of capacitor and bit-line at same level and its fabrication method for 8F2 DRAM cell with minimum bit-line coupling noise
Grant 6,373,090 - Chi April 16, 2 | 2002-04-16 |
Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications
Grant 6,362,012 - Chi , et al. March 26, 2 | 2002-03-26 |
Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate
Grant 6,288,943 - Chi September 11, 2 | 2001-09-11 |
Transistor and logic circuit of thin silicon-on-insulator wafers based on gate induced drain leakage currents
Grant 6,281,550 - Chi August 28, 2 | 2001-08-28 |
Vertical Bipolar Transistor Based On Gate Induced Drain Leakage Current
App 20010013610 - CHI, MIN-HWA ; et al. | 2001-08-16 |
Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process
Grant 6,271,084 - Tu , et al. August 7, 2 | 2001-08-07 |
Single polysilicon DRAM cell and array with current gain
Grant 6,262,447 - Chi July 17, 2 | 2001-07-17 |
DRAM cell and array to store two-bit data having merged stack capacitor and trench capacitor
Grant 6,184,548 - Chi , et al. February 6, 2 | 2001-02-06 |
Flash memory cell using p+/N-well diode with double poly floating gate
Grant 6,181,601 - Chi January 30, 2 | 2001-01-30 |
Edge triggered delay line, a multiple adjustable delay line circuit, and an application of same
Grant 6,175,605 - Chi January 16, 2 | 2001-01-16 |
Method for forming a crown capacitor having HSG for DRAM memory
Grant 6,174,770 - Chi January 16, 2 | 2001-01-16 |
Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise
Grant 6,174,767 - Chi January 16, 2 | 2001-01-16 |
Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor
Grant 6,171,923 - Chi , et al. January 9, 2 | 2001-01-09 |
CMOS inverter using gate induced drain leakage current
Grant 6,144,075 - Chi November 7, 2 | 2000-11-07 |
Method for forming flash memory of ETOX-cell programmed by band-to-band tunneling induced substrate hot electron and read by gate induced drain leakage current
Grant 6,143,607 - Chi November 7, 2 | 2000-11-07 |
NOR array architecture and operation methods for ETOX cells capable of full EEPROM functions
Grant 6,133,604 - Chi October 17, 2 | 2000-10-17 |
Electron injection method for substrate-hot-electron program and erase V.sub.T tightening for ETOX cell
Grant 6,091,635 - Chi , et al. July 18, 2 | 2000-07-18 |
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