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Patent applications and USPTO patent grants for Chi; Kuang.The latest application filed is for "high speed interface for a programmable interconnect circuit".
Patent | Date |
---|---|
SERDES with programmable I/O architecture Grant 7,327,160 - Agrawal , et al. February 5, 2 | 2008-02-05 |
SERDES with programmable I/O architecture Grant 7,208,975 - Agrawal , et al. April 24, 2 | 2007-04-24 |
Scalable serializer-deserializer architecture and programmable interface Grant 7,098,685 - Agrawal , et al. August 29, 2 | 2006-08-29 |
Clock data recovery deserializer with programmable SYNC detect logic Grant 6,999,543 - Trinh , et al. February 14, 2 | 2006-02-14 |
Digital phase locked loop with programmable digital filter Grant 6,993,108 - Chi , et al. January 31, 2 | 2006-01-31 |
High speed interface for a programmable interconnect circuit Grant 6,861,868 - Agrawal , et al. March 1, 2 | 2005-03-01 |
Programmable interconnect circuit with a phase-locked loop Grant 6,661,254 - Agrawal , et al. December 9, 2 | 2003-12-09 |
High speed interface for a programmable interconnect circuit Grant 6,650,141 - Agrawal , et al. November 18, 2 | 2003-11-18 |
High Speed Interface For A Programmable Interconnect Circuit App 20030112031 - Agrawal, Om P. ;   et al. | 2003-06-19 |
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