Chheda; Sejal N.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Chheda; Sejal N..The latest application filed is for "method of forming an integrated circuit device using dummy features and structure thereof".
- Chheda; Sejal N. - Austin TX
| Patent | Date |
|---|---|
| Semiconductor tiling structure and method of formation Grant 6,614,062 - Chheda , et al. September 2, 2 | 2003-09-02 |
| Method of forming an integrated circuit device using dummy features and structure thereof Grant 6,611,045 - Travis , et al. August 26, 2 | 2003-08-26 |
| Method of forming an integrated circuit device using dummy features and structure thereof App 20020179902 - Travis, Edward O. ; et al. | 2002-12-05 |
| Selective sizing of features to compensate for resist thickness variations in semiconductor devices Grant 6,489,083 - Smith , et al. December 3, 2 | 2002-12-03 |
| Semiconductor device, a process for a semiconductor device, and a process for making a masking database Grant 6,459,156 - Travis , et al. October 1, 2 | 2002-10-01 |
| Semiconductor tiling structure and method of formation App 20020093071 - Chheda, Sejal N. ; et al. | 2002-07-18 |
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