Cherabuddi; Rajasekhar

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cherabuddi; Rajasekhar.The latest application filed is for "methods and systems for hardware acceleration of database operations and queries based on multiple hardware accelerators".

Company Profile

0.19.4

Cherabuddi; Rajasekhar - Saratoga CA
Cherabuddi; Rajasekhar - Cupertino CA
Cherabuddi; Rajasekhar - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and systems for hardware acceleration of streamed database operations and queries based on multiple hardware accelerators Grant 9,141,670 - Branscome , et al. September 22, 2	2015-09-22
Methods and systems for hardware acceleration of database operations and queries based on multiple hardware accelerators Grant 8,468,151 - Branscome , et al. June 18, 2	2013-06-18
Methods And Systems For Hardware Acceleration Of Database Operations And Queries Based On Multiple Hardware Accelerators App 20120054236 - Branscome; Jeremy L. ; et al.	2012-03-01
Methods And Systems For Hardware Acceleration Of Streamed Database Operations And Queries Based On Multiple Hardware Accelerators App 20120047126 - Branscome; Jeremy L. ; et al.	2012-02-23
Isolation of data, control, and management traffic in a storage area network Grant 7,433,351 - Pelissier , et al. October 7, 2	2008-10-07
Yield improvement through probe-based cache size reduction Grant 6,918,071 - Cherabuddi , et al. July 12, 2	2005-07-12
Dynamically allocated cache memory for a multi-processor unit Grant 6,725,336 - Cherabuddi April 20, 2	2004-04-20
Yield improvement through probe-based cache size reduction App 20030088811 - Cherabuddi, Rajasekhar ; et al.	2003-05-08
DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domains Grant 6,553,435 - Normoyle , et al. April 22, 2	2003-04-22
Dynamically allocated cache memory for a multi-processor unit App 20020184445 - Cherabuddi, Rajasekhar	2002-12-05
Simplified writeback handling Grant 6,477,622 - Normoyle , et al. November 5, 2	2002-11-05
Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures Grant 6,330,662 - Patel , et al. December 11, 2	2001-12-11
Bi-level branch target prediction scheme with fetch address prediction Grant 6,134,654 - Patel , et al. October 17, 2	2000-10-17
Bi-level branch target prediction scheme with mux select prediction Grant 6,115,810 - Patel , et al. September 5, 2	2000-09-05
Inclusion vector architecture for a level two cache Grant 5,996,048 - Cherabuddi , et al. November 30, 1	1999-11-30
Superscalar processor for retiring multiple instructions in working register file by changing the status bits associated with each execution result to identify valid data Grant 5,944,810 - Cherabuddi August 31, 1	1999-08-31
Method and apparatus for branch target prediction Grant 5,938,761 - Patel , et al. August 17, 1	1999-08-17
Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor Grant 5,884,100 - Normoyle , et al. March 16, 1	1999-03-16
Apparatus and method to improve primary memory latencies using an eviction buffer to store write requests Grant 5,860,117 - Cherabuddi January 12, 1	1999-01-12
Cache memory array which stores two-way set associative data Grant 5,854,761 - Patel , et al. December 29, 1	1998-12-29
Apparatus and method to efficiently abort and restart a primary memory access Grant 5,829,010 - Cherabuddi October 27, 1	1998-10-27

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