Chengson; David P.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Chengson; David P..The latest application filed is for "multi-interface compatible bus over a common physical connection".
- Chengson; David P. - Aptos CA
- Chengson; David P. - Scotts Valley CA US
- Chengson; David P. - Mountain View CA
| Patent | Date |
|---|---|
| Electrical signature fault detection Grant 11,156,651 - Chengson , et al. October 26, 2 | 2021-10-26 |
| Grid array pattern for crosstalk reduction Grant 10,455,690 - Chengson , et al. Oc | 2019-10-22 |
| Grid array pattern for crosstalk reduction Grant 10,455,691 - Chengson Oc | 2019-10-22 |
| Placement of vias in printed circuit board circuits Grant 10,383,213 - Chengson , et al. A | 2019-08-13 |
| Electrical signature fault detection Grant 10,365,314 - Chengson , et al. July 30, 2 | 2019-07-30 |
| Placement of vias in printed circuit board circuits Grant 10,231,325 - Chengson , et al. | 2019-03-12 |
| Systems and methods for error detection and correction Grant 10,069,596 - Chengson , et al. September 4, 2 | 2018-09-04 |
| Digital bit insertion for clock recovery Grant 9,237,003 - Chengson , et al. January 12, 2 | 2016-01-12 |
| Multi-interface Compatible Bus Over A Common Physical Connection App 20130215911 - Chengson; David P. ; et al. | 2013-08-22 |
| Testing vias formed in printed circuit boards Grant 8,508,248 - Chengson August 13, 2 | 2013-08-13 |
| Low latency serial memory interface Grant 8,452,908 - Chengson , et al. May 28, 2 | 2013-05-28 |
| Multi-interface compatible bus over a common physical connection Grant 8,411,695 - Chengson , et al. April 2, 2 | 2013-04-02 |
| Error-free startup of low phase noise oscillators Grant 8,164,392 - Chengson , et al. April 24, 2 | 2012-04-24 |
| Validating High Speed Link Performance Margin For Switch Fabric With Any-to-any Connection Across A Midplane App 20110267073 - CHENGSON; David P. ; et al. | 2011-11-03 |
| Error-free Startup Of Low Phase Noise Oscillators App 20110260769 - CHENGSON; David P. ; et al. | 2011-10-27 |
| Low Latency Serial Memory Interface App 20110161544 - Chengson; David P. ; et al. | 2011-06-30 |
| Processor-inclusive memory module Grant 5,867,419 - Chengson , et al. February 2, 1 | 1999-02-02 |
| Multi-configurable push-pull/open-drain driver circuit Grant 5,811,997 - Chengson , et al. September 22, 1 | 1998-09-22 |
| System and method to reduce jitter in digital delay-locked loops Grant 5,790,612 - Chengson , et al. August 4, 1 | 1998-08-04 |
| Processor-inclusive memory module Grant 5,710,733 - Chengson , et al. January 20, 1 | 1998-01-20 |
| Self-calibrating clock synchronization system Grant 5,036,528 - Le , et al. July 30, 1 | 1991-07-30 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 