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Semiconductor device and method of manufacture
Grant 11,410,929 - Chang , et al. August 9, 2 | 2022-08-09 |
Package Structure And Method For Forming The Same
App 20220246509 - CHIEN; CHIN-HER ; et al. | 2022-08-04 |
Package structure and method for forming the same
Grant 11,387,177 - Chien , et al. July 12, 2 | 2022-07-12 |
Interposer with capacitors
Grant 11,367,695 - Chang , et al. June 21, 2 | 2022-06-21 |
Integrated Circuit With Mixed Row Heights
App 20220149033 - SIO; Kam-Tou ; et al. | 2022-05-12 |
Integrated circuit with mixed row heights
Grant 11,282,829 - Sio , et al. March 22, 2 | 2022-03-22 |
Standard Cells And Variations Thereof Within A Standard Cell Library
App 20220067266 - CHEN; Sheng-Hsiung ; et al. | 2022-03-03 |
Method Of Forming Merged Pillar Structures And Method Of Generating Layout Diagram Of Same
App 20220043957 - BISWAS; Hiranmay ; et al. | 2022-02-10 |
Standard cells and variations thereof within a standard cell library
Grant 11,182,533 - Chen , et al. November 23, 2 | 2021-11-23 |
Hybrid Sheet Layout, Method, System, And Structure
App 20210357565 - FANG; Shang-Wei ; et al. | 2021-11-18 |
Method for making a semiconductor device
Grant 11,170,150 - Chang , et al. November 9, 2 | 2021-11-09 |
Merged pillar structures and method of generating layout diagram of same
Grant 11,157,677 - Biswas , et al. October 26, 2 | 2021-10-26 |
Electromagnetic Shielding Metal-insulator-metal Capacitor Structure
App 20210320072 - LEE; Hui Yu ; et al. | 2021-10-14 |
Semiconductor device with filler cell region, method of generating layout diagram and system for same
Grant 11,138,360 - Huang , et al. October 5, 2 | 2021-10-05 |
Method For Manufacturing A Cell Having Pins And Semiconductor Device Based On Same
App 20210294957 - SUE; Pin-Dai ; et al. | 2021-09-23 |
Entangled Inductor Structures
App 20210257156 - CHANG; Ka Fai ; et al. | 2021-08-19 |
Electromagnetic shielding metal-insulator-metal capacitor structure
Grant 11,088,084 - Lee , et al. August 10, 2 | 2021-08-10 |
Through-Silicon Vias in Integrated Circuit Packaging
App 20210173998 - CHANG; Fong-yuan ; et al. | 2021-06-10 |
Method for generating layout diagram including cell having pin patterns and semiconductor device based on same
Grant 11,030,372 - Sue , et al. June 8, 2 | 2021-06-08 |
Structure and Method for Cooling Three-Dimensional Integrated Circuits
App 20210159225 - Lee; Hui-Yu ; et al. | 2021-05-27 |
Semiconductor Device and Method of Manufacture
App 20210082816 - Chang; Fong-yuan ; et al. | 2021-03-18 |
Through-silicon vias in integrated circuit packaging
Grant 10,949,597 - Chang , et al. March 16, 2 | 2021-03-16 |
Entangled inductor structures
Grant 10,943,729 - Chang , et al. March 9, 2 | 2021-03-09 |
Interconnect Structure, Semiconductor Structure Including Interconnect Structure And Method For Forming The Same
App 20210066223 - TSAI; JUNG-CHOU ; et al. | 2021-03-04 |
Structure and method for cooling three-dimensional integrated circuits
Grant 10,910,365 - Lee , et al. February 2, 2 | 2021-02-02 |
Method And System Of Forming Integrated Circuit
App 20200402856 - CHANG; KA FAI ; et al. | 2020-12-24 |
Package Structure And Method For Forming The Same
App 20200395281 - CHIEN; CHIN-HER ; et al. | 2020-12-17 |
Integrated Circuit With Mixed Row Heights
App 20200357786 - SIO; Kam-Tou ; et al. | 2020-11-12 |
Method and system of forming integrated circuit
Grant 10,811,316 - Chang , et al. October 20, 2 | 2020-10-20 |
Standard Cells And Variations Thereof Within A Standard Cell Library
App 20200328202 - CHEN; Sheng-Hsiung ; et al. | 2020-10-15 |
Structure and method for cooling three-dimensional integrated circuits
Grant 10,763,253 - Lee , et al. Sep | 2020-09-01 |
Electromagnetic Shielding Metal-insulator-metal Capacitor Structure
App 20200258846 - A1 | 2020-08-13 |
Standard cells and variations thereof within a standard cell library
Grant 10,741,539 - Chen , et al. A | 2020-08-11 |
Techniques based on electromigration characteristics of cell interconnect
Grant 10,678,990 - Yang , et al. | 2020-06-09 |
Merged Pillar Structures And Method Of Generating Layout Diagram Of Same
App 20200175220 - BISWAS; Hiranmay ; et al. | 2020-06-04 |
Soic Chip Architecture
App 20200168527 - CHANG; Fong-Yuan ; et al. | 2020-05-28 |
Electromagnetic shielding metal-insulator-metal capacitor structure
Grant 10,665,550 - Lee , et al. | 2020-05-26 |
Method For Making A Semiconductor Device
App 20200151382 - CHANG; Chi-Wen ; et al. | 2020-05-14 |
Method For Generating Layout Diagram Including Cell Having Pin Patterns And Semiconductor Device Based On Same
App 20200134124 - SUE; Pin-Dai ; et al. | 2020-04-30 |
Semiconductor Device With Filler Cell Region, Method Of Generating Layout Diagram And System For Same
App 20200134125 - HUANG; Po-Hsiang ; et al. | 2020-04-30 |
Entangled Inductor Structures
App 20200135388 - CHANG; Ka Fai ; et al. | 2020-04-30 |
Method And System Of Forming Integrated Circuit
App 20200051863 - CHANG; KA FAI ; et al. | 2020-02-13 |
Interposer With Capacitors
App 20200043873 - CHANG; Fong-yuan ; et al. | 2020-02-06 |
System for manufacturing a semiconductor device
Grant 10,540,475 - Chang , et al. Ja | 2020-01-21 |
Through-silicon Vias In Integrated Circuit Packaging
App 20200019668 - CHANG; Fong-yuan ; et al. | 2020-01-16 |
Electromagnetic Shielding Metal-insulator-metal Capacitor Structure
App 20200020644 - LEE; Hui Yu ; et al. | 2020-01-16 |
Structure and Method for Cooling Three-Dimensional Integrated Circuits
App 20200006325 - Lee; Hui Yu ; et al. | 2020-01-02 |
Merged pillar structures and method of generating layout diagram of same
Grant 10,515,178 - Biswas , et al. Dec | 2019-12-24 |
Method For Generating Layout Diagram Including Wiring Arrangement
App 20190286784 - CHANG; Fong-Yuan ; et al. | 2019-09-19 |
Circuit with combined cells and method for manufacturing the same
Grant 10,396,063 - Chang , et al. A | 2019-08-27 |
Techniques Based On Electromigration Characteristics Of Cell Interconnect
App 20190108304 - Yang; Kuo-Nan ; et al. | 2019-04-11 |
Standard Cells and Variations Thereof Within a Standard Cell Library
App 20190064770 - CHEN; Sheng-Hsiung ; et al. | 2019-02-28 |
Merged Pillar Structures And Method Of Generating Layout Diagram Of Same
App 20190065653 - BISWAS; Hiranmay ; et al. | 2019-02-28 |
System For Manufacturing A Semiconductor Device
App 20190034578 - CHANG; Chi-Wen ; et al. | 2019-01-31 |
Semiconductor structure
Grant 10,163,787 - Lee , et al. Dec | 2018-12-25 |
Method and apparatus of a three dimensional integrated circuit
Grant 10,157,252 - Chang , et al. Dec | 2018-12-18 |
Techniques based on electromigration characteristics of cell interconnect
Grant 10,157,254 - Yang , et al. Dec | 2018-12-18 |
Method of manufacturing a semiconductor device
Grant 10,095,827 - Chang , et al. October 9, 2 | 2018-10-09 |
Method Of Manufacturing A Semiconductor Device
App 20180225407 - CHANG; Chi-Wen ; et al. | 2018-08-09 |
Method and apparatus for modeling multi-terminal MOS device for LVS and PDK
Grant 9,984,196 - Wei , et al. May 29, 2 | 2018-05-29 |
Method and system for manufacturing a semiconductor device
Grant 9,934,352 - Chang , et al. April 3, 2 | 2018-04-03 |
Structure and Method for Cooling Three-Dimensional Integrated Circuits
App 20170358572 - Lee; Hui-Yu ; et al. | 2017-12-14 |
Circuit With Combined Cells And Method For Manufacturing The Same
App 20170345809 - CHANG; FONG-YUAN ; et al. | 2017-11-30 |
Semiconductor Structure
App 20170300611 - LEE; Hui Yu ; et al. | 2017-10-19 |
Methods for double-patterning-compliant standard cell design
Grant 9,747,402 - Chen , et al. August 29, 2 | 2017-08-29 |
Structure and method for cooling three-dimensional integrated circuits
Grant 9,748,228 - Lee , et al. August 29, 2 | 2017-08-29 |
Semiconductor structure having a plurality of conductive paths
Grant 9,698,099 - Lee , et al. July 4, 2 | 2017-07-04 |
Techniques Based On Electromigration Characteristics Of Cell Interconnect
App 20170186691 - Yang; Kuo-Nan ; et al. | 2017-06-29 |
Optimization for circuit migration
Grant 9,672,315 - Lu , et al. June 6, 2 | 2017-06-06 |
Method and Apparatus for Modeling Multi-terminal MOS Device for LVS and PDK
App 20160267218 - Wei; Chau-Wen ; et al. | 2016-09-15 |
Method and Apparatus of a Three Dimensional Integrated Circuit
App 20160259877 - Chang; Chi-Wen ; et al. | 2016-09-08 |
Variation modeling
Grant 9,367,654 - Chang , et al. June 14, 2 | 2016-06-14 |
Method and apparatus for modeling multi-terminal MOS device for LVS and PDK
Grant 9,361,425 - Wei , et al. June 7, 2 | 2016-06-07 |
RC corner solutions for double patterning technology
Grant 9,361,423 - Su , et al. June 7, 2 | 2016-06-07 |
Method and apparatus of a three dimensional integrated circuit
Grant 9,355,205 - Chang , et al. May 31, 2 | 2016-05-31 |
Parasitic component library and method for efficient circuit design and simulation using the same
Grant 9,348,965 - Chen , et al. May 24, 2 | 2016-05-24 |
Multi-patterning system and method using pre-coloring or locked patterns
Grant 9,335,624 - Lee , et al. May 10, 2 | 2016-05-10 |
Double patterning technology (DPT) layout routing
Grant 9,317,650 - Chen , et al. April 19, 2 | 2016-04-19 |
Method And System For Manufacturing A Semiconductor Device
App 20160070839 - CHANG; Chi-Wen ; et al. | 2016-03-10 |
Optimization for circuit migration
Grant 9,275,186 - Lu , et al. March 1, 2 | 2016-03-01 |
RC extraction for single patterning spacer technique
Grant 9,262,558 - Huang , et al. February 16, 2 | 2016-02-16 |
Method of generating a simulation model of a predefined fabrication process
Grant 9,230,052 - Ho , et al. January 5, 2 | 2016-01-05 |
Variation Modeling
App 20150379174 - Chang; Chi-Wen ; et al. | 2015-12-31 |
Method, system and computer program product for designing semiconductor device
Grant 9,213,797 - Chang , et al. December 15, 2 | 2015-12-15 |
Multiple via connections using connectivity rings
Grant 9,213,795 - Hsu , et al. December 15, 2 | 2015-12-15 |
Variation factor assignment
Grant 9,129,082 - Chang , et al. September 8, 2 | 2015-09-08 |
Method of designing fin field effect transistor (FinFET)-based circuit and system for implementing the same
Grant 9,122,833 - Chen , et al. September 1, 2 | 2015-09-01 |
Semiconductor Structure
App 20150228576 - LEE; Hui Yu ; et al. | 2015-08-13 |
Method and Apparatus for Modeling Multi-terminal MOS Device for LVS and PDK
App 20150213190 - Wei; Chau-Wen ; et al. | 2015-07-30 |
Method and Apparatus of a Three Dimensional Integrated Circuit
App 20150179568 - Chang; Chi-Wen ; et al. | 2015-06-25 |
Semiconductor structure and method of generating masks for making integrated circuit
Grant 9,053,255 - Lee , et al. June 9, 2 | 2015-06-09 |
Method, System And Computer Program Product For Designing Semiconductor Device
App 20150143311 - CHANG; Chi-Wen ; et al. | 2015-05-21 |
Method Of Designing Fin Field Effect Transistor (finfet)-based Circuit And System For Implementing The Same
App 20150143314 - CHEN; Chin-Sheng ; et al. | 2015-05-21 |
Multi-patterning conflict free integrated circuit design
Grant 9,026,971 - Ho , et al. May 5, 2 | 2015-05-05 |
Multi-patterning System And Method
App 20150121317 - LEE; Hui Yu ; et al. | 2015-04-30 |
Method and apparatus for modeling multi-terminal MOS device for LVS and PDK
Grant 9,000,524 - Wei , et al. April 7, 2 | 2015-04-07 |
Methods for Double-Patterning-Compliant Standard Cell Design
App 20150095870 - Chen; Huang-Yu ; et al. | 2015-04-02 |
Parasitic Component Library And Method For Efficient Circuit Design And Simulation Using The Same
App 20150074629 - CHEN; Chin-Sheng ; et al. | 2015-03-12 |
Method and system for replacing a pattern in a layout
Grant 8,977,991 - Chen , et al. March 10, 2 | 2015-03-10 |
Structure And Method For Cooling Three-dimensional Integrated Circuits
App 20150060039 - LEE; HUI-YU ; et al. | 2015-03-05 |
Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment
Grant 8,972,919 - Chen , et al. March 3, 2 | 2015-03-03 |
Method Of Generating A Simulation Model Of A Predefined Fabrication Process
App 20150052493 - HO; Chia-Ming ; et al. | 2015-02-19 |
Double Patterning Technology (dpt) Layout Routing
App 20150012895 - Chen; Huang-Yu ; et al. | 2015-01-08 |
Methods for double-patterning-compliant standard cell design
Grant 8,907,441 - Chen , et al. December 9, 2 | 2014-12-09 |
Semiconductor device design method, system and computer-readable medium
Grant 8,904,337 - Yang , et al. December 2, 2 | 2014-12-02 |
Parasitic component library and method for efficient circuit design and simulation using the same
Grant 8,893,066 - Chen , et al. November 18, 2 | 2014-11-18 |
Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process
Grant 8,887,106 - Ho , et al. November 11, 2 | 2014-11-11 |
RC Corner Solutions for Double Patterning Technology
App 20140304670 - Su; Ke-Ying ; et al. | 2014-10-09 |
Integrated circuit layout modification
Grant 8,856,696 - Chen , et al. October 7, 2 | 2014-10-07 |
Method of radio-frequency and microwave device generation
Grant 8,856,701 - Chen , et al. October 7, 2 | 2014-10-07 |
Standard Cell Design Layout
App 20140298284 - Hsu; Chin-Hsiung ; et al. | 2014-10-02 |
Double patterning technology (DPT) layout routing
Grant 8,850,368 - Chen , et al. September 30, 2 | 2014-09-30 |
Method Of Radio-frequency And Microwave Device Generation
App 20140282308 - Chen; Chin-Sheng ; et al. | 2014-09-18 |
Parasitic Capacitance Extraction for FinFETs
App 20140258962 - Ho; Chia-Ming ; et al. | 2014-09-11 |
Parasitic capacitance extraction for FinFETs
Grant 8,826,213 - Ho , et al. September 2, 2 | 2014-09-02 |
Design Optimization for Circuit Migration
App 20140245251 - Lu; Lee-Chung ; et al. | 2014-08-28 |
Variation Factor Assignment
App 20140245242 - Chang; Chi-Wen ; et al. | 2014-08-28 |
Multiple via connections using connectivity rings
Grant 8,813,016 - Hsu , et al. August 19, 2 | 2014-08-19 |
Double Patterning Technology (dpt) Layout Routing
App 20140215428 - Chen; Huang-Yu ; et al. | 2014-07-31 |
Decomposition and marking of semiconductor device design layout in double patterning lithography
Grant 8,775,977 - Hsu , et al. July 8, 2 | 2014-07-08 |
Parasitic Component Library And Method For Efficient Circuit Design And Simulation Using The Same
App 20140189623 - CHEN; Chin-Sheng ; et al. | 2014-07-03 |
Semiconductor Device Design Method, System And Computer-readable Medium
App 20140189635 - YANG; Ching-Shun ; et al. | 2014-07-03 |
RC corner solutions for double patterning technology
Grant 8,751,975 - Su , et al. June 10, 2 | 2014-06-10 |
Method and system for photomask assignment for double patterning technology
Grant 8,732,628 - Wu , et al. May 20, 2 | 2014-05-20 |
Semiconductor device design method, system and computer-readable medium
Grant 8,707,245 - Yang , et al. April 22, 2 | 2014-04-22 |
Method and system for semiconductor simulation
Grant 8,707,230 - Hu , et al. April 22, 2 | 2014-04-22 |
Semiconductor Structure And Method Of Generating Masks For Making Integrated Circuit
App 20140103545 - LEE; Hui Yu ; et al. | 2014-04-17 |
Discrete device modeling
Grant 8,694,938 - Yang , et al. April 8, 2 | 2014-04-08 |
Method of generating RC technology file
Grant 8,671,382 - Su , et al. March 11, 2 | 2014-03-11 |
Static Timing Analysis Method And System Considering Capacitive Coupling And Double Patterning Mask Misalignment
App 20140068537 - CHEN; Wen-Hao ; et al. | 2014-03-06 |
Method And System For Replacing A Pattern In A Layout
App 20140059504 - CHEN; Huang-Yu ; et al. | 2014-02-27 |
Multi-patterning method
Grant 8,645,877 - Hsu , et al. February 4, 2 | 2014-02-04 |
Integrated circuit design using DFM-enhanced architecture
Grant 8,631,366 - Hou , et al. January 14, 2 | 2014-01-14 |
Static Timing Analysis Method And System Considering Capacitive Coupling And Double Patterning Mask Misalignment
App 20140013292 - CHEN; Wen-Hao ; et al. | 2014-01-09 |
Discrete Device Modeling
App 20140007028 - Yang; Ching-Shun ; et al. | 2014-01-02 |
System and method for reducing layout-dependent effects
Grant 8,621,409 - Lee , et al. December 31, 2 | 2013-12-31 |
Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment
Grant 8,612,912 - Chen , et al. December 17, 2 | 2013-12-17 |
Method and system for replacing a pattern in a layout
Grant 8,601,408 - Chen , et al. December 3, 2 | 2013-12-03 |
Method of circuit design yield analysis
Grant 8,601,416 - Kuo , et al. December 3, 2 | 2013-12-03 |
System And Method For Reducing Layout-dependent Effects
App 20130290916 - LEE; Hui Yu ; et al. | 2013-10-31 |
RC Corner Solutions for Double Patterning Technology
App 20130275927 - Su; Ke-Ying ; et al. | 2013-10-17 |
Multi-patterning Method
App 20130254726 - HSU; Chin-Chang ; et al. | 2013-09-26 |
Method Of Circuit Design Yield Analysis
App 20130246986 - KUO; Chin-Cheng ; et al. | 2013-09-19 |
Rc Extraction For Single Patterning Spacer Technique
App 20130239070 - HUANG; Cheng-I ; et al. | 2013-09-12 |
Semiconductor Device Design Method, System And Computer-readable Medium
App 20130227501 - YANG; Ching-Shun ; et al. | 2013-08-29 |
Method of Generating RC Technology File
App 20130227514 - Su; Ke-Ying ; et al. | 2013-08-29 |
Coloring/grouping Patterns For Multi-patterning
App 20130205266 - Chen; Wen-Hao ; et al. | 2013-08-08 |
Integrated Circuit Layout Modification
App 20130191796 - CHEN; Wen-Hao ; et al. | 2013-07-25 |
Systems and methods for creating frequency-dependent RC extraction netlist
Grant 8,495,532 - Su , et al. July 23, 2 | 2013-07-23 |
Method Of Generating A Bias-adjusted Layout Design Of A Conductive Feature And Method Of Generating A Simulation Model Of A Predefined Fabrication Process
App 20130174112 - HO; Chia-Ming ; et al. | 2013-07-04 |
Multi-patterning method
Grant 8,473,873 - Hsu , et al. June 25, 2 | 2013-06-25 |
Multi-patterning method
Grant 8,468,470 - Hsu , et al. June 18, 2 | 2013-06-18 |
Systems and methods for creating frequency-dependent netlist
Grant 8,453,095 - Su , et al. May 28, 2 | 2013-05-28 |
RC extraction for single patterning spacer technique
Grant 8,448,120 - Huang , et al. May 21, 2 | 2013-05-21 |
Tool and method for eliminating multi-patterning conflicts
Grant 8,448,100 - Lin , et al. May 21, 2 | 2013-05-21 |
Methodology for analysis and fixing guidance of pre-coloring layout
Grant 8,434,043 - Hsu , et al. April 30, 2 | 2013-04-30 |
Method And System For Replacing A Pattern In A Layout
App 20130091476 - CHEN; Huang-Yu ; et al. | 2013-04-11 |
Advisory system for verifying sensitive circuits in chip-design
Grant 8,418,098 - Huang , et al. April 9, 2 | 2013-04-09 |
Method of generating RC technology file
Grant 8,418,112 - Su , et al. April 9, 2 | 2013-04-09 |
Chip-level ECO shrink
Grant 8,418,117 - Chen , et al. April 9, 2 | 2013-04-09 |
Multi-patterning Method
App 20130074018 - HSU; Chin-Chang ; et al. | 2013-03-21 |
Multi-patterning Method
App 20130061186 - HSU; Chin-Chang ; et al. | 2013-03-07 |
Systems And Methods For Creating Frequency-dependent Netlist
App 20130014070 - SU; Ke-Ying ; et al. | 2013-01-10 |
IC design flow enhancement with CMP simulation
Grant 8,336,002 - Chang , et al. December 18, 2 | 2012-12-18 |
Routing method for double patterning design
Grant 8,327,301 - Cheng , et al. December 4, 2 | 2012-12-04 |
Rc Extraction For Single Patterning Spacer Technique
App 20120288786 - Huang; Cheng-I ; et al. | 2012-11-15 |
Method and Apparatus for Modeling Multi-terminal MOS Device for LVS and PDK
App 20120256271 - Wei; Chau-Wen ; et al. | 2012-10-11 |
Systematic method for variable layout shrink
Grant 8,286,119 - Hsu , et al. October 9, 2 | 2012-10-09 |
Systems And Methods For Creating Frequency-dependent Rc Extraction Netlist
App 20120254811 - SU; Ke-Ying ; et al. | 2012-10-04 |
Method of Generating RC Technology File
App 20120226479 - Su; Ke-Ying ; et al. | 2012-09-06 |
Methods for cell boundary isolation in double patterning design
Grant 8,255,837 - Lu , et al. August 28, 2 | 2012-08-28 |
Mask-shift-aware RC extraction for double patterning design
Grant 8,252,489 - Su , et al. August 28, 2 | 2012-08-28 |
Decomposition And Marking Of Semiconductor Device Design Layout In Double Patterning Lithography
App 20120210279 - HSU; Chin-Chang ; et al. | 2012-08-16 |
Double patterning friendly lithography method and system
Grant 8,245,174 - Cheng , et al. August 14, 2 | 2012-08-14 |
Routing system and method for double patterning technology
Grant 8,239,806 - Chen , et al. August 7, 2 | 2012-08-07 |
Methods for E-beam direct write lithography
Grant 8,214,773 - Lu , et al. July 3, 2 | 2012-07-03 |
Table-based DFM for accurate post-layout analysis
Grant 8,201,111 - Hou , et al. June 12, 2 | 2012-06-12 |
System and method for design-for-manufacturability data encryption
Grant 8,136,168 - Cheng , et al. March 13, 2 | 2012-03-13 |
Mask-shift-aware Rc Extraction For Double Patterning Design
App 20120052422 - Lu; Lee-Chung ; et al. | 2012-03-01 |
Mask-Shift-Aware RC Extraction for Double Patterning Design
App 20120054696 - Su; Ke-Ying ; et al. | 2012-03-01 |
Mask-shift-aware RC extraction for double patterning design
Grant 8,119,310 - Lu , et al. February 21, 2 | 2012-02-21 |
Table-Based DFM for Accurate Post-Layout Analysis
App 20110289466 - Hou; Yung-Chin ; et al. | 2011-11-24 |
Method for shape and timing equivalent dimension extraction
Grant 8,037,575 - Cheng , et al. October 18, 2 | 2011-10-18 |
Table-based DFM for accurate post-layout analysis
Grant 8,001,494 - Hou , et al. August 16, 2 | 2011-08-16 |
Methods for Double-Patterning-Compliant Standard Cell Design
App 20110193234 - Chen; Huang-Yu ; et al. | 2011-08-11 |
Routing System And Method For Double Patterning Technology
App 20110119648 - Chen; Huang-Yu ; et al. | 2011-05-19 |
Chip-Level ECO Shrink
App 20110072405 - Chen; Huang-Yu ; et al. | 2011-03-24 |
Design Optimization for Circuit Migration
App 20110035717 - Lu; Lee-Chung ; et al. | 2011-02-10 |
Double Patterning Friendly Lithography Method And System
App 20110023002 - Cheng; Yi-Kan ; et al. | 2011-01-27 |
Integrated Circuit Design using DFM-Enhanced Architecture
App 20100281446 - Hou; Yung-Chin ; et al. | 2010-11-04 |
Method for smart dummy insertion to reduce run time and dummy count
Grant 7,801,717 - Chang , et al. September 21, 2 | 2010-09-21 |
Design Methods for E-Beam Direct Write Lithography
App 20100205577 - Lu; Lee-Chung ; et al. | 2010-08-12 |
Systematic Method for Variable Layout Shrink
App 20100199238 - Hsu; Fu-Chieh ; et al. | 2010-08-05 |
Routing Method for Double Patterning Design
App 20100199253 - Cheng; Yi-Kan ; et al. | 2010-08-05 |
Methods for Cell Boundary Isolation in Double Patterning Design
App 20100196803 - Lu; Lee-Chung ; et al. | 2010-08-05 |
Method, apparatus, and system for LPC hot spot fix
Grant 7,725,861 - Cheng , et al. May 25, 2 | 2010-05-25 |
Table-based Dfm For Accurate Post-layout Analysis
App 20100095253 - HOU; Yung-Chin ; et al. | 2010-04-15 |
Method For Shape And Timing Equivalent Dimension Extraction
App 20090222785 - CHENG; Ying-Chou ; et al. | 2009-09-03 |
Advisory System for Verifying Sensitive Circuits in Chip-Design
App 20090172617 - Huang; Chi-Heng ; et al. | 2009-07-02 |
Secure Yield-aware Design Flow with Annotated Design Libraries
App 20090055782 - Fu; Chung-Min ; et al. | 2009-02-26 |
Sanity checker for integrated circuits
Grant 7,467,365 - Chang , et al. December 16, 2 | 2008-12-16 |
Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count
App 20080176343 - Chang; Gwan Sin ; et al. | 2008-07-24 |
Sanity checker for integrated circuits
App 20080072191 - Chang; George H. ; et al. | 2008-03-20 |
Metal Thickness Simulation for Improving RC Extraction Accuracy
App 20070266360 - Cheng; Yi-Kan ; et al. | 2007-11-15 |
Method, Apparatus, and System for LPC Hot Spot Fix
App 20070266352 - Cheng; Yi-Kan ; et al. | 2007-11-15 |
System and Method for Design-for-Manufacturability Data Encryption
App 20070266248 - Cheng; Yi-Kan ; et al. | 2007-11-15 |
IC Design Flow Enhancement With CMP Simulation
App 20070266356 - Chang; Gwan Sin ; et al. | 2007-11-15 |
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