Cheng; Chi Fung

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cheng; Chi Fung.The latest application filed is for "dedicated interface architecture for a hybrid integrated circuit".

Company Profile

0.24.1

Cheng; Chi Fung - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for removing a pulse having a different pulse width relative to that of other pulses in a clock signal of an analog to digital converter Grant 8,994,407 - Cheng , et al. March 31, 2	2015-03-31
Dedicated interface architecture for a hybrid integrated circuit Grant 8,990,757 - Chan , et al. March 24, 2	2015-03-24
Method and system for precompensation of data output Grant 8,693,117 - Cheng April 8, 2	2014-04-08
Non-volatile memory devices having uniform error distributions among pages Grant 8,638,604 - Cheng January 28, 2	2014-01-28
Data channel circuit with reference clock signal free of glitches Grant 8,558,580 - Cheng , et al. October 15, 2	2013-10-15
Method and apparatus for write precompensation in a magnetic recording system Grant 8,358,478 - Cheng January 22, 2	2013-01-22
Deglitch circuit removing glitches from input clock signal Grant 8,319,524 - Cheng , et al. November 27, 2	2012-11-27
High bandwidth phase locked loop (PLL) with feedback loop including a frequency divider Grant 7,898,306 - Cheng March 1, 2	2011-03-01
Method and apparatus for write precompensation in a magnetic recording system Grant 7,880,986 - Cheng February 1, 2	2011-02-01
Apparatus for low-jitter frequency and phase locked loop and associated methods Grant 7,825,737 - Fang , et al. November 2, 2	2010-11-02
Apparatus, method, and system for correction of baseline wander Grant 7,589,649 - Aga , et al. September 15, 2	2009-09-15
Method and apparatus for write precompensation in a magnetic recording system Grant 7,583,459 - Cheng September 1, 2	2009-09-01
Precompensation circuit for magnetic recording Grant 7,515,368 - Sutardja , et al. April 7, 2	2009-04-07
High bandwidth phase locked pool (PLL) Grant 7,427,883 - Cheng September 23, 2	2008-09-23
Dedicated Interface Architecture For A Hybrid Integrated Circuit App 20080204074 - Chan; King W. ; et al.	2008-08-28
Dedicated interface architecture for a hybrid integrated circuit Grant 7,389,487 - Chan , et al. June 17, 2	2008-06-17
Asymmetric compensation circuit Grant 7,242,545 - Cheng July 10, 2	2007-07-10
Precompensation circuit for magnetic recording Grant 7,184,231 - Sutardja , et al. February 27, 2	2007-02-27
Asymmetric compensation circuit Grant 7,161,752 - Cheng January 9, 2	2007-01-09
High bandwidth phase locked loop (PLL) Grant 7,116,144 - Cheng October 3, 2	2006-10-03
Precompensation circuit for magnetic recording Grant 6,956,708 - Sutardja , et al. October 18, 2	2005-10-18
Precompensation circuit for magnetic recording Grant 6,721,114 - Sutardja , et al. April 13, 2	2004-04-13
High speed inductor current driver with minimum overshoot Grant 6,429,987 - Cheng August 6, 2	2002-08-06

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