Cheng; Chan-Chi Jason

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cheng; Chan-Chi Jason.The latest application filed is for "redundant configuration memory systems and methods".

Company Profile

0.15.1

Cheng; Chan-Chi Jason - Fremont CA US
Cheng; Chan-Chi Jason - Shanghai CN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Testing of soft error detection logic for programmable logic devices Grant 8,370,691 - Cheng , et al. February 5, 2	2013-02-05
Soft error detection logic testing systems and methods Grant 8,065,574 - Cheng , et al. November 22, 2	2011-11-22
Compression and decompression of configuration data using repeated data frames Grant 8,058,898 - Cheng , et al. November 15, 2	2011-11-15
Compression and decompression of configuration data using repeated data frames Grant 7,902,865 - Cheng , et al. March 8, 2	2011-03-08
Redundant configuration memory systems and methods Grant 7,746,107 - Singh , et al. June 29, 2	2010-06-29
Multiplexer initialization systems and methods Grant 7,663,401 - Nguyen , et al. February 16, 2	2010-02-16
Redundant configuration memory systems and methods Grant 7,598,765 - Singh , et al. October 6, 2	2009-10-06
High fan-out signal routing systems and methods Grant 7,576,563 - Wei , et al. August 18, 2	2009-08-18
Programmable logic device with enhanced logic block architecture Grant 7,573,291 - Agrawal , et al. August 11, 2	2009-08-11
Redundant Configuration Memory Systems And Methods App 20080204073 - Singh; Satwant ; et al.	2008-08-28
Programmable logic device with enhanced logic block architecture Grant 7,295,035 - Agrawal , et al. November 13, 2	2007-11-13
FIFO memory with programmable data port widths Grant 6,986,004 - Cheng , et al. January 10, 2	2006-01-10
CPLD with multi-function blocks and distributed memory Grant 6,879,182 - Agrawal , et al. April 12, 2	2005-04-12
Cascaded logic block architecture for complex programmable logic devices Grant 6,861,871 - Agrawal , et al. March 1, 2	2005-03-01
Non-volatile and reconfigurable programmable logic devices Grant 6,828,823 - Tsui , et al. December 7, 2	2004-12-07

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