Chene; Mon-Ren

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chene; Mon-Ren.The latest application filed is for "verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single fpga".

Company Profile

0.8.5

Chene; Mon-Ren - Cupertino CA
Chene; Mon-Ren - Saratoga CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single FPGA Grant 9,032,344 - Chene May 12, 2	2015-05-12
Verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single FPGA App 20140013163 - CHENE; Mon-Ren	2014-01-09
Verification module apparatus to serve as a prototype for functionally debugging an electronic design that exceeds the capacity of a single FPGA Grant 8,607,174 - Chene December 10, 2	2013-12-10
Verification module apparatus to serve as a prototype for functionally debugging an electronic design that exceeds the capacity of a single FPGA App 20130179850 - Chene; Mon-Ren	2013-07-11
Logic verification module apparatus to serve as a hyper prototype for debugging an electronic design that exceeds the capacity of a single FPGA Grant 8,356,272 - Chene January 15, 2	2013-01-15
Logic Verification Module Apparatus To Serve As A Hyper Prototype For Debugging An Electronic Design That Exceeds The Capacity Of A Single Fpga App 20120290993 - Chene; Mon-Ren	2012-11-15
Scalable reconfigurable prototyping system and method Grant 7,353,162 - Huang , et al. April 1, 2	2008-04-01
Scalable reconfigurable prototyping system and method App 20060184350 - Huang; Thomas B. ; et al.	2006-08-17
Timing driven method for laying out a user's circuit onto a programmable integrated circuit device Grant 5,521,837 - Frankle , et al. May 28, 1	1996-05-28
Logic placement using positionally asymmetrical partitioning method Grant 5,513,124 - Trimberger , et al. April 30, 1	1996-04-30

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