Chen; Yueh-Hsin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Yueh-Hsin.The latest application filed is for "self-aligned source for split-gate non-volatile memory cell".

Company Profile

0.5.9

Chen; Yueh-Hsin - Pleasanton CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-aligned source for split-gate non-volatile memory cell Grant 9,659,946 - Su , et al. May 23, 2	2017-05-23
Method of forming a self-aligned stack gate structure for use in a non-volatile memory array Grant 9,570,581 - Toren , et al. February 14, 2	2017-02-14
Self-Aligned Source For Split-Gate Non-volatile Memory Cell App 20170025424 - Su; Chien-Sheng ; et al.	2017-01-26
Formation of self-aligned source for split-gate non-volatile memory cell Grant 9,484,261 - Su , et al. November 1, 2	2016-11-01
Method of Forming A Self-Aligned Stack Gate Structure For Use In A Non-volatile Memory Array App 20160225878 - Toren; Willem-Jan ; et al.	2016-08-04
Self-aligned stack gate structure for use in a non-volatile memory array and a method of forming such structure Grant 9,330,922 - Toren , et al. May 3, 2	2016-05-03
Method Of Forming Extended Source-Drain MOS Transistors App 20150270372 - SU; CHIEN-SHENG ; et al.	2015-09-24
Formation Of Self-Aligned Source For Split-Gate Non-volatile Memory Cell App 20150008451 - Su; Chien-Sheng ; et al.	2015-01-08
Method Of Making High-Voltage MOS Transistors With Thin Poly Gate App 20140273387 - Su; Chien-Sheng ; et al.	2014-09-18
Extended Source-Drain MOS Transistors And Method Of Formation App 20140084367 - Su; Chien-Sheng ; et al.	2014-03-27
Self-Aligned Stack Gate Structure For Use In A Non-volatile Memory Array And A Method Of Forming Such Structure App 20130234223 - Toren; Willem-Jan ; et al.	2013-09-12

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