loadpatents
name:-0.020606994628906
name:-0.0098979473114014
name:-0.0077090263366699
Chen; Yen-Pin Patent Filings

Chen; Yen-Pin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Yen-Pin.The latest application filed is for "method of generating netlist including proximity-effect-inducer (pei) parameters".

Company Profile
11.16.19
  • Chen; Yen-Pin - Taipei TW
  • CHEN; Yen-Pin - Hsinchu TW
  • CHEN; YEN-PIN - KAOHSIUNG CITY TW
  • Chen; Yen-Pin - Taipei City TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated circuit having a high cell density
Grant 11,437,319 - Chen , et al. September 6, 2
2022-09-06
Method Of Generating Netlist Including Proximity-effect-inducer (pei) Parameters
App 20220245318 - CHEN; Yen-Pin ;   et al.
2022-08-04
Embedded Memory System And Memory Testing Method
App 20220206704 - CHEN; YEN-PIN
2022-06-30
Method Of Obtaining Advice Data Of Physiological Characteristics For A Patient In Order To Lower Risk Of The Patient Entering A Medical Emergency State
App 20220130550 - CHEN; YEN-PIN ;   et al.
2022-04-28
Method and system for sigma-based timing optimization
Grant 11,176,305 - Chen , et al. November 16, 2
2021-11-16
Systems And Methods For Context Aware Circuit Design
App 20210334447 - Hsu; Li-Chung ;   et al.
2021-10-28
Systems and methods for context aware circuit design
Grant 11,068,637 - Hsu , et al. July 20, 2
2021-07-20
Integrated Circuit Having a High Cell Density
App 20210028108 - Chen; Sheng-Hsiung ;   et al.
2021-01-28
Integrated circuit having a high cell density
Grant 10,804,200 - Chen , et al. October 13, 2
2020-10-13
Method And System For Sigma-based Timing Optimization
App 20200279068 - CHEN; YEN-PIN ;   et al.
2020-09-03
Method and system for sigma-based timing optimization
Grant 10,678,989 - Chen , et al.
2020-06-09
Method of timing analysis
Grant 10,515,166 - Chen , et al. Dec
2019-12-24
Characterizing cell using input waveforms with different tail characteristics
Grant 10,467,364 - Tam , et al. No
2019-11-05
Integrated Circuit Having a High Cell Density
App 20190096805 - Chen; Sheng-Hsiung ;   et al.
2019-03-28
Semiconductor circuit design and manufacture method
Grant 10,176,284 - Hsu , et al. J
2019-01-08
Circuit design method and system
Grant 10,169,506 - Wang , et al. J
2019-01-01
Integrated circuit having a high cell density
Grant 10,157,840 - Chen , et al. Dec
2018-12-18
Method And System For Sigma-based Timing Optimization
App 20180247007 - CHEN; YEN-PIN ;   et al.
2018-08-30
Method Of Timing Analysis
App 20180232474 - CHEN; YEN-PIN ;   et al.
2018-08-16
Integrated Circuit Having a High Cell Density
App 20180158776 - Chen; Sheng-Hsiung ;   et al.
2018-06-07
Design Method
App 20180096087 - HSU; LI-CHUNG ;   et al.
2018-04-05
Characterizing Cell Using Input Waveforms With Different Tail Characteristics
App 20170116361 - TAM; KING-HO ;   et al.
2017-04-27
Circuit Design Method And System
App 20170039310 - WANG; Chung-Hsing ;   et al.
2017-02-09
Characterizing cell using input waveform generation considering different circuit topologies
Grant 9,563,734 - Tam , et al. February 7, 2
2017-02-07
Method of generating techfile having reduced corner variation value
Grant 9,477,803 - Wang , et al. October 25, 2
2016-10-25
Method Of Generating Techfile Having Reduced Corner Variation Value
App 20160034631 - WANG; Chung-Hsing ;   et al.
2016-02-04
Characterizing Cell Using Input Waveform Geneartion Considering Different Circuit Topoloiges
App 20150193569 - TAM; KING-HO ;   et al.
2015-07-09
Layout re-decomposition for multiple patterning layouts
Grant 8,914,755 - Hsu , et al. December 16, 2
2014-12-16
Layout Re-decomposition For Multiple Patterning Layouts
App 20140359544 - Hsu; Chin-Hsiung ;   et al.
2014-12-04
Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed
Grant 8,826,212 - Yeh , et al. September 2, 2
2014-09-02
Method Of Forming A Layout Including Cells Having Different Threshold Voltages, A System Of Implementing And A Layout Formed
App 20140165020 - YEH; Sung-Yen ;   et al.
2014-06-12
Cell-context aware integrated circuit design
Grant 8,677,292 - Fu , et al. March 18, 2
2014-03-18
Cell-Context Aware Integrated Circuit Design
App 20100275167 - Fu; Chung-Min ;   et al.
2010-10-28

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