Chen; Yaochung

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Yaochung.The latest application filed is for "wrap around gate field effect transistor (wagfet)".

Company Profile

0.10.5

Chen; Yaochung - Rancho Palos Verdes CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Wrap around gate field effect transistor (WAGFET) Grant 9,882,000 - Sarkozy , et al. January 30, 2	2018-01-30
Wrap Around Gate Field Effect Transistor (wagfet) App 20170345895 - SARKOZY; STEPHEN J. ; et al.	2017-11-30
Vertical cavity surface emitting laser with composite reflectors Grant 9,735,545 - Chen , et al. August 15, 2	2017-08-15
Active input load wide bandwidth low noise HEMT amplifier Grant 7,612,610 - Chen November 3, 2	2009-11-03
Club Extension To A T-gate High Electron Mobility Transistor App 20090267115 - Namba; Carol Osaka ; et al.	2009-10-29
Club extension to a T-gate high electron mobility transistor Grant 7,608,865 - Namba , et al. October 27, 2	2009-10-27
Active input load wide bandwidth low noise hemt amplifier App 20070090879 - Chen; Yaochung	2007-04-26
Wafer thinning techniques Grant 6,764,573 - Lai , et al. July 20, 2	2004-07-20
Hybrid semi-physical and data fitting HEMT modeling approach for large signal and non-linear microwave/millimeter wave circuit CAD Grant 6,711,723 - Tsai , et al. March 23, 2	2004-03-23
Wafer adhesive for semiconductor dry etch applications Grant 6,551,905 - Barsky , et al. April 22, 2	2003-04-22
Wafer thinning techniques App 20030071009 - Lai, Richard ; et al.	2003-04-17
Enhancement mode device Grant 6,452,221 - Lai , et al. September 17, 2	2002-09-17
Hybrid semi-physical and data fitting HEMT modeling approach for large signal and non-linear microwave/millimeter wave circuit CAD App 20020083406 - Tsai, Roger S. ; et al.	2002-06-27
Method for determining etch depth Grant 6,383,826 - Barsky , et al. May 7, 2	2002-05-07
Combining network to implement a power amplifier having monolithically integrated planar interconnect and transistors Grant 6,259,335 - Ingram , et al. July 10, 2	2001-07-10

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.