Chen; Yan-Chun
Patent Applications and Registrations
Patent applications and USPTO patent grants for Chen; Yan-Chun.The latest application filed is for "method for optimizing an integrated circuit layout design".
- Chen; Yan-Chun - Kaohsiung TW
- Chen; Yan-Chun - Kaohsiung City TW
| Patent | Date |
|---|---|
| Pattern verifying method Grant 9,785,046 - Hsieh , et al. October 10, 2 | 2017-10-10 |
| Method for optimizing an integrated circuit layout design Grant 9,747,404 - Kuo , et al. August 29, 2 | 2017-08-29 |
| Method For Optimizing An Integrated Circuit Layout Design App 20170024506 - Kuo; Shih-Ming ; et al. | 2017-01-26 |
| Pattern Verifying Method App 20160147140 - Hsieh; Te-Hsien ; et al. | 2016-05-26 |
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