loadpatents
name:-0.014714002609253
name:-0.015829086303711
name:-0.00054097175598145
Chen; Tung-Po Patent Filings

Chen; Tung-Po

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Tung-Po.The latest application filed is for "manufacturing method of non-volatile memory".

Company Profile
0.13.9
  • Chen; Tung-Po - Taichung TW
  • Chen, Tung-Po - Taichung City TW
  • Chen; Tung-Po - Tai-Chung TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Manufacturing Method Of Non-volatile Memory
App 20090186459 - Chen; Tung-Po
2009-07-23
Method for manufacturing gate dielectric layer
Grant 7,273,787 - Chen , et al. September 25, 2
2007-09-25
Method For Manufacturing Gate Dielectric Layer
App 20060281251 - Chen; Wen-Ji ;   et al.
2006-12-14
Method For Manufacturing One-time Electrically Programmable Read Only Memory
App 20060154418 - Chang; Ko-Hsing ;   et al.
2006-07-13
Method for manufacturing one-time electrically programmable read only memory
Grant 7,074,674 - Chang , et al. July 11, 2
2006-07-11
Method Of Fabricating A Gate Oxide Layer
App 20060030136 - Chen; Tung-Po
2006-02-09
Non-volatile Memory And Manufacturing Method Thereof
App 20060019445 - Chen; Tung-Po
2006-01-26
Process for forming high temperature stable self-aligned metal silicide layer
Grant 6,670,249 - Pan , et al. December 30, 2
2003-12-30
Method of forming a titanium-containing glue layer
App 20030186532 - Chen, Tung-Po ;   et al.
2003-10-02
Method for reducing thermal budget in node contact application
App 20020025678 - Chen, Tung-Po ;   et al.
2002-02-28
Salicide formation process
App 20020025676 - Chen, Tung-Po ;   et al.
2002-02-28
Method of forming a MOS transistor
Grant 6,297,112 - Lin , et al. October 2, 2
2001-10-02
Method of fabricating field effect transistor
App 20010010962 - Chen, Tung-Po ;   et al.
2001-08-02
Method of fabricating CMOS using Si-B layer to form source/drain extension junction
Grant 6,255,152 - Chen July 3, 2
2001-07-03
Method of fabricating field effect transistor
Grant 6,228,730 - Chen , et al. May 8, 2
2001-05-08
Method of forming salicide in embedded dynamic random access memory
Grant 6,225,155 - Lin , et al. May 1, 2
2001-05-01
Method for forming polycide dual gate
Grant 6,197,672 - Lin , et al. March 6, 2
2001-03-06
Method for fabricating an embedded dynamic random access memory using self-aligned silicide technology
Grant 6,133,130 - Lin , et al. October 17, 2
2000-10-17
Planarization on an embedded dynamic random access memory
Grant 6,060,349 - Peng , et al. May 9, 2
2000-05-09
Salicide formation process
Grant 6,022,795 - Chen , et al. February 8, 2
2000-02-08
Self-aligned silicide manufacturing method
Grant 5,893,751 - Jenq , et al. April 13, 1
1999-04-13
Method of manufacturing self-aligned silicide
Grant 5,858,849 - Chen January 12, 1
1999-01-12

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