Chen; Sho Long

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Sho Long.The latest application filed is for "risc microprocessor architecture implementing multiple typed register sets".

Company Profile

0.10.6

Chen; Sho Long - Saratoga CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
RISC microprocessor architecture implementing multiple typed register sets Grant 7,941,636 - Garg , et al. May 10, 2	2011-05-10
RISC Microprocessor Architecture Implementing Multiple Typed Register Sets App 20100106942 - GARG; Sanjiv ; et al.	2010-04-29
RISC microprocessor architecture implementing multiple typed register sets Grant 7,685,402 - Garg , et al. March 23, 2	2010-03-23
RISC microprocessor architecture implementing multiple typed register sets Grant 7,555,631 - Garg , et al. June 30, 2	2009-06-30
Video encoding using variable bit rates Grant 7,409,097 - Zhang , et al. August 5, 2	2008-08-05
RISC microprocessor architecture implementing multiple typed register sets App 20070113047 - Garg; Sanjiv ; et al.	2007-05-17
Motion estimation using predetermined pixel patterns and subpatterns Grant 6,934,332 - Auyeung , et al. August 23, 2	2005-08-23
Video encoding using variable bit rates App 20050105815 - Zhang, Dengzhi ; et al.	2005-05-19
Multi-phase motion estimation system and method Grant 6,891,890 - Auyeung , et al. May 10, 2	2005-05-10
Motion estimation using multiple search windows Grant 6,813,315 - Auyeung , et al. November 2, 2	2004-11-02
Video encoding using direct mode predicted frames App 20030202590 - Gu, Qunshan ; et al.	2003-10-30
RISC microprocessor architecture implementing multiple typed register sets App 20030115440 - Garg, Sanjiv ; et al.	2003-06-19
RISC microprocessor architecture implementing multiple register sets App 20010034823 - Garg, Sanjiv ; et al.	2001-10-25
RISC microprocessor architecture implementing multiple typed register sets Grant 5,838,986 - Garg , et al. November 17, 1	1998-11-17
Hybrid hierarchial/full-search MPEG encoder motion estimation Grant 5,731,850 - Maturi , et al. March 24, 1	1998-03-24
RISC microprocessor architecture implementing multiple typed register sets Grant 5,682,546 - Garg , et al. October 28, 1	1997-10-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.