Chen; Roawen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Roawen.The latest application filed is for "package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate".

Company Profile

0.16.10

Chen; Roawen - San Jose CA
Chen; Roawen - San Diego CA
Chen; Roawen - Monte Sereno CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate Grant 9,768,144 - Wu , et al. September 19, 2	2017-09-19
Half node scaling for vertical structures Grant 9,478,541 - Song , et al. October 25, 2	2016-10-25
Recessed semiconductor substrates and associated techniques Grant 9,391,045 - Wu , et al. July 12, 2	2016-07-12
Package Assembly Including A Semiconductor Substrate In Which A First Portion Of A Surface Of The Semiconductor Substrate Is Recessed Relative To A Second Portion Of The Surface Of The Semiconductor Substrate To Form A Recessed Region In The Semiconductor Substrate App 20160155732 - Wu; Albert ; et al.	2016-06-02
Half Node Scaling For Vertical Structures App 20160071847 - SONG; Stanley Seungchul ; et al.	2016-03-10
Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate Grant 9,257,410 - Wu , et al. February 9, 2	2016-02-09
Recessed Semiconductor Substrates And Associated Techniques App 20150279806 - Wu; Albert ; et al.	2015-10-01
Recessed semiconductor substrates and associated techniques Grant 9,034,730 - Wu , et al. May 19, 2	2015-05-19
Solid-state disk with wireless functionality Grant 8,935,464 - Sutardja , et al. January 13, 2	2015-01-13
Low Cost Interposer Comprising An Oxidation Layer App 20140306349 - Gu; Shiqun ; et al.	2014-10-16
Techniques And Configurations For Recessed Semiconductor Substrates App 20140124961 - WU; Albert ; et al.	2014-05-08
Solid-state disk with wireless functionality Grant 8,719,485 - Sutardja , et al. May 6, 2	2014-05-06
Method for fabricating 1T-DRAM on bulk silicon Grant 8,008,137 - Wu , et al. August 30, 2	2011-08-30
Recessed Semiconductor Substrates App 20110186998 - Wu; Albert ; et al.	2011-08-04
Techniques And Configurations For Recessed Semiconductor Substrates App 20110186960 - Wu; Albert ; et al.	2011-08-04
Recessed Semiconductor Substrates And Associated Techniques App 20110186992 - Wu; Albert ; et al.	2011-08-04
Methods of making and using fuse structures, and integrated circuits including the same Grant 7,820,493 - Cheng , et al. October 26, 2	2010-10-26
Fuse structures, methods of making and using the same, and integrated circuits including the same Grant 7,704,805 - Cheng , et al. April 27, 2	2010-04-27
Solid-state Disk With Wireless Functionality App 20090327588 - Sutardja; Sehat ; et al.	2009-12-31
Fuse structures, methods of making and using the same, and integrated circuits including the same Grant 7,589,363 - Cheng , et al. September 15, 2	2009-09-15
Fuse structures, methods of making and using the same, and integrated circuits including the same Grant 7,344,924 - Cheng , et al. March 18, 2	2008-03-18
Method For Fabricating 1t-dram On Bulk Silicon App 20070215906 - Wu; Albert ; et al.	2007-09-20
Fuse structures, methods of making and using the same, and integrated circuits including the same Grant 6,940,107 - Cheng , et al. September 6, 2	2005-09-06

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.