Chen; Min-Liang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Min-Liang.The latest application filed is for "stacked semiconductor device and method".

Company Profile

0.17.4

Chen; Min-Liang - Hsinchu TW
CHEN; Min-Liang - Hsinchu City TW
Chen; Min-Liang - Hsin-Chu TW
Chen; Min-Liang - Allentown PA
Chen; Min-Liang - Wescosville PA
Chen; Min-Liang - Lower Macungie Township Lehigh County

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stacked semiconductor device and method Grant 7,897,431 - Chen , et al. March 1, 2	2011-03-01
Stacked Semiconductor Device And Method App 20100038802 - CHEN; Min-Liang ; et al.	2010-02-18
Method of fabricating high-voltage mos having doubled-diffused drain App 20090011561 - Chen; Min-Liang	2009-01-08
Method of forming a gate oxide layer App 20090011564 - Chen; Min-Liang	2009-01-08
High density memory structure App 20010028075 - Chen, Min-Liang ; et al.	2001-10-11
Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation Grant 6,100,561 - Wang , et al. August 8, 2	2000-08-08
Self-registered cylindrical capacitor of high density DRAMs Grant 5,885,866 - Chen March 23, 1	1999-03-23
Semiconductor having self-aligned polysilicon electrode layer Grant 5,880,496 - Chen , et al. March 9, 1	1999-03-09
Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation Grant 5,827,747 - Wang , et al. October 27, 1	1998-10-27
Method of forming a bit-line and a capacitor structure in an integrated circuit Grant 5,792,686 - Chen , et al. August 11, 1	1998-08-11
Double-poly monos flash EEPROM cell Grant 5,703,388 - Wang , et al. December 30, 1	1997-12-30
Method of fabricating a capacitor over a bit line DRAM process Grant 5,691,223 - Pittikoun , et al. November 25, 1	1997-11-25
Through glass ROM code implant to reduce product delivering time Grant 5,681,772 - Chen , et al. October 28, 1	1997-10-28
Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology Grant 5,573,965 - Chen , et al. November 12, 1	1996-11-12
Transistor with inverse silicide T-gate structure Grant 5,290,720 - Chen March 1, 1	1994-03-01
Integrated circuit with planar dielectric layer Grant 5,200,358 - Bollinger , et al. April 6, 1	1993-04-06
Contact metallization of semiconductor integrated-circuit devices Grant 5,102,827 - Chen , et al. April 7, 1	1992-04-07
CMOS integrated circuit having improved isolation Grant 5,045,898 - Chen , et al. September 3, 1	1991-09-03
Method of making electrical contacts to gate structures in integrated circuits Grant 4,996,167 - Chen February 26, 1	1991-02-26
Integrated circuit with improved tub tie Grant 4,905,073 - Chen , et al. February 27, 1	1990-02-27
Method of making silicides by heating in oxygen to remove contamination Grant 4,886,765 - Chen , et al. December 12, 1	1989-12-12

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