Chen; Ker-Min

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Ker-Min.The latest application filed is for "intellectual property recommending method and system".

Company Profile

0.31.34

Chen; Ker-Min - Hsinchu City TW
Chen; Ker-Min - Hsin-Chu TW
Chen; Ker-Min - Hsinchu N/A TW
Chen; Ker-Min - Hsin chu City TW
Chen, Ker-Min - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Intellectual Property Recommending Method And System App 20210390644 - Chen; Ker-Min ; et al.	2021-12-16
Automatic application-rule checker Grant 8,943,453 - Chen , et al. January 27, 2	2015-01-27
Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof Grant 8,501,622 - Chen August 6, 2	2013-08-06
Integrated Circuit Having Input/output Cell Array Having Single Gate Orientation App 20130194004 - CHEN; Ker-Min	2013-08-01
Integrated circuit having input/output cell array having single gate orientation Grant 8,492,795 - Chen July 23, 2	2013-07-23
Automatic Application-Rule Checker App 20110055778 - Chen; Ker-Min ; et al.	2011-03-03
Low leakage voltage level shifting circuit Grant 7,884,643 - Wang , et al. February 8, 2	2011-02-08
Method for automatically routing multi-voltage multi-pitch metal lines Grant 7,865,852 - Chen January 4, 2	2011-01-04
Method and system for setup/hold characterization in sequential cells Grant 7,795,939 - Chen , et al. September 14, 2	2010-09-14
Semiconductor Device with Two or More Bond Pad Connections for Each Input/Output Cell and Method of Manufacture Thereof App 20100190299 - Chen; Ker-Min	2010-07-29
Method and System for Setup/Hold Characterization in Sequential Cells App 20100164583 - Chen; Ker-Min ; et al.	2010-07-01
Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof Grant 7,714,362 - Chen May 11, 2	2010-05-11
Low Leakage Voltage Level Shifting Circuit App 20100026366 - Wang; Guang-Cheng ; et al.	2010-02-04
Fine Pitch Bond Pad Structure App 20100013109 - Chen; Ker-Min	2010-01-21
ESD protection system for multiple-domain integrated circuits Grant 7,649,214 - Chen January 19, 2	2010-01-19
Ultra fine pitch I/O design for microchips Grant 7,594,198 - Chen September 22, 2	2009-09-22
Serpentine ballasting resistors for multi-finger ESD protection device Grant 7,557,413 - Chen July 7, 2	2009-07-07
System and method for reducing design cycle time for designing input/output cells Grant 7,500,214 - Chen , et al. March 3, 2	2009-03-03
Method for Automatically Routing Multi-Voltage Multi-Pitch Metal Lines App 20090024976 - Chen; Ker-Min	2009-01-22
ESD protection system for multi-power domain circuitry Grant 7,420,789 - Chen September 2, 2	2008-09-02
Ultra fine pitch I/O design for microchips App 20080204113 - Chen; Ker-Min	2008-08-28
ESD protection system for multi-power domain circuitry Grant 7,417,837 - Chen August 26, 2	2008-08-26
System and Method For Implementing An Online Design Platform For Integrated Circuits App 20080184174 - Chen; Ker-Min	2008-07-31
Serpentine ballasting resistors for multi-finger ESD protection device App 20080111193 - Chen; Ker-Min	2008-05-15
Dual voltage single gate oxide I/O circuit with high voltage stress tolerance Grant 7,362,136 - Chen April 22, 2	2008-04-22
Method and apparatus for inter-chip wireless communication Grant 7,330,702 - Chen , et al. February 12, 2	2008-02-12
Regenerative power-on control circuit Grant 7,295,052 - Chen November 13, 2	2007-11-13
Dual voltage single gate oxide I/O circuit with high voltage stress tolerance App 20070247190 - Chen; Ker-Min	2007-10-25
Gate-coupled ESD protection circuit for high voltage tolerant I/O Grant 7,274,544 - Chen , et al. September 25, 2	2007-09-25
Dual-voltage three-state buffer circuit with simplified tri-state level shifter Grant 7,248,076 - Chen , et al. July 24, 2	2007-07-24
Cascaded gate-driven ESD clamp Grant 7,221,551 - Chen May 22, 2	2007-05-22
Tie-high and tie-low circuit Grant 7,221,183 - Chen May 22, 2	2007-05-22
EDS protection system for multi-power domain circuitry App 20070091522 - Chen; Ker-Min	2007-04-26
ESD protection system for multi-power domain circuitry App 20070091523 - Chen; Ker-Min	2007-04-26
ESD protection system for multiple-domain integrated circuits App 20070085144 - Chen; Ker-Min	2007-04-19
Single gate oxide I/O buffer with improved under-drive feature Grant 7,193,441 - Chen , et al. March 20, 2	2007-03-20
Regenerative power-on control circuit App 20070030039 - Chen; Ker-Min	2007-02-08
Input buffer structure with single gate oxide Grant 7,173,472 - Chen , et al. February 6, 2	2007-02-06
Built-in test circuit for an integrated circuit device Grant 7,168,021 - Chen January 23, 2	2007-01-23
Integrated circuit for level-shifting voltage levels Grant 7,151,391 - Chen , et al. December 19, 2	2006-12-19
Boost-biased level shifter Grant 7,151,400 - Chen December 19, 2	2006-12-19
High-voltage-tolerant feedback coupled I/O buffer Grant 7,142,017 - Chen November 28, 2	2006-11-28
Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof App 20060214189 - Chen; Ker-Min	2006-09-28
System And Method For Reducing Design Cycle Time For Designing Input/output Cells App 20060195811 - Chen; Ker-Min ; et al.	2006-08-31
Tie-high and tie-low circuit App 20060186925 - Chen; Ker-Min	2006-08-24
Dual-voltage three-state buffer circuit with simplified tri-state level shifter App 20060186921 - Chen; Kuo-Ji ; et al.	2006-08-24
Built-in Test Circuit for an Integrated Circuit Device App 20060174173 - Chen; Ker-Min	2006-08-03
Method and apparatus for inter-chip wireless communication App 20060172719 - Chen; Ker-Min ; et al.	2006-08-03
Semiconductor device and method of manufacture thereof with two or more bond pad connections for each input/output cell Grant 7,071,561 - Chen July 4, 2	2006-07-04
System and method for reducing design cycle time for designing input/output cells Grant 7,062,740 - Chen , et al. June 13, 2	2006-06-13
Single gate oxide I/O buffer with improved under-drive feature App 20060103435 - Chen; Kuo-Ji ; et al.	2006-05-18
Gate-coupled ESD protection circuit for high voltage tolerant I/O App 20060087779 - Chen; Ker-Min ; et al.	2006-04-27
High-voltage-tolerant feedback coupled I/O buffer App 20060049847 - Chen; Ker-Min	2006-03-09
Boost-biased level shifter App 20060012415 - Chen; Ker-Min	2006-01-19
Cascaded gate-driven ESD clamp App 20050275989 - Chen, Ker-Min	2005-12-15
Semiconductor device and method of manufacture thereof with two or more bond pad connections for each input/output cell App 20050269705 - Chen, Ker-Min	2005-12-08
Input buffer structure with single gate oxide App 20050270079 - Chen, Kuo-Ji ; et al.	2005-12-08
USB interface and testing method thereof App 20050097403 - Chen, Ker-Min	2005-05-05
System and method for reducing design cycle time for designing input/output cells App 20040237059 - Chen, Ker-Min ; et al.	2004-11-25
Circuit to eliminate bus contention at chip power up App 20030042946 - Chen, Ker-Min ; et al.	2003-03-06
Chip-area-efficient pattern and method of hierarchal power routing App 20020048923 - Chen, Ker-Min	2002-04-25

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