loadpatents
name:-0.010170936584473
name:-0.0068349838256836
name:-0.0055480003356934
Chen; Juan Yi Patent Filings

Chen; Juan Yi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Juan Yi.The latest application filed is for "method and system for integrated circuit design with on-chip variation and spatial correlation".

Company Profile
5.6.7
  • Chen; Juan Yi - Hsinchu TW
  • Chen; Juan Yi - Hsinchu City TW
  • Chen; Juan Yi - Hsin-Chu TW
  • Chen; Juan-Yi - Chiai TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method and system for integrated circuit design with on-chip variation and spatial correlation
Grant 10,860,769 - Chiang , et al. December 8, 2
2020-12-08
Method and System for Integrated Circuit Design With On-Chip Variation and Spatial Correlation
App 20200125782 - Chiang; Katherine ;   et al.
2020-04-23
Method and system for integrated circuit design with on-chip variation and spatial correlation
Grant 10,521,538 - Chiang , et al. Dec
2019-12-31
Method For Establishing Aging Model Of Device And Analyzing Aging State Of Device With Aging Model
App 20190065648 - HUANG; Yi-Shun ;   et al.
2019-02-28
Method for establishing aging model of device and analyzing aging state of device with aging model
Grant 10,216,879 - Huang , et al. Feb
2019-02-26
Simulation scheme including self heating effect
Grant 10,019,545 - Jeng , et al. July 10, 2
2018-07-10
Method and System for Integrated Circuit Design With On-Chip Variation and Spatial Correlation
App 20170316138 - Chiang; Katherine ;   et al.
2017-11-02
Simulation Scheme Including Self Heating Effect
App 20150363526 - Jeng; Min-Chie ;   et al.
2015-12-17
Method of fabricating spacers and cleaning method of post-etching and semiconductor device
Grant 7,642,152 - Wang , et al. January 5, 2
2010-01-05
Method Of Fabricating Spacers And Cleaning Method Of Post-etching And Semiconductor Device
App 20080036018 - Wang; Chuan-Kai ;   et al.
2008-02-14
Method of fabricating spacers and cleaning method of post-etching and semiconductor device
App 20070054458 - Wang; Chuan-Kai ;   et al.
2007-03-08
Gap-filling process
Grant 6,833,318 - Weng , et al. December 21, 2
2004-12-21
Gap-filling process
App 20040097069 - Weng, Chun-Jen ;   et al.
2004-05-20

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed