Chen; Jong

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Jong.The latest application filed is for "mechanism for forming mems device".

Company Profile

0.16.6

Chen; Jong - Hsinchu TW
CHEN; Jong - Hsinchu City TW
Chen; Jong - Taipei TW
Chen, Jong - Hsin-Chu TW
Chen; Jong - Chung-Ho City Taipei Hsien TW
Chen; Jong - Science-Based Industrial Park Hsin-Chu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Mechanism for forming MEMS device Grant 9,090,452 - Cheng , et al. July 28, 2	2015-07-28
Mechanism For Forming Mems Device App 20150158716 - CHENG; Shyh-Wei ; et al.	2015-06-11
Via layout with via groups placed in interlocked arrangement Grant 7,459,792 - Chen December 2, 2	2008-12-02
Via layout with via groups placed in interlocked arrangement App 20070290361 - Chen; Jong	2007-12-20
Stacked-gate flash memory cell with folding gate and increased coupling ratio Grant 6,724,036 - Hsieh , et al. April 20, 2	2004-04-20
Tilt-angle ion implant to improve junction breakdown in flash memory application App 20030166324 - Lin, Chrong-Jung ; et al.	2003-09-04
Method for reducing light reflectance in a photolithographic process App 20030044726 - Chen, Jong ; et al.	2003-03-06
Easy-to-assembly LED display for any graphics and text Grant 6,448,900 - Chen September 10, 2	2002-09-10
Flash memory cell with vertically oriented channel Grant 6,437,397 - Lin , et al. August 20, 2	2002-08-20
Tilt-angle ion implant to improve junction breakdown in flash memory application App 20020019103 - Lin, Chrong-Jung ; et al.	2002-02-14
Tilt-angle ion implant to improve junction breakdown in flash memory application Grant 6,297,098 - Lin , et al. October 2, 2	2001-10-02
Method to fabricate a flash memory cell with a planar stacked gate App 20010012661 - Lin, Chong Jung ; et al.	2001-08-09
Implant method to improve characteristics of high voltage isolation and high voltage breakdown Grant 6,251,744 - Su , et al. June 26, 2	2001-06-26
Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby Grant 6,172,395 - Chen , et al. January 9, 2	2001-01-09
Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices Grant 6,133,096 - Su , et al. October 17, 2	2000-10-17
Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process Grant 6,130,168 - Chu , et al. October 10, 2	2000-10-10
Thin ONO thickness control and gradual gate oxidation suppression by b. N.su2 treatment in flash memory Grant 6,127,227 - Lin , et al. October 3, 2	2000-10-03
Method for making deep sub-micron mosfet structures having improved electrical characteristics Grant 6,124,177 - Lin , et al. September 26, 2	2000-09-26
Vertical channels in split-gate flash memory cell Grant 6,078,076 - Lin , et al. June 20, 2	2000-06-20
Method of making embedded flash memory with salicide and sac structure Grant 6,074,915 - Chen , et al. June 13, 2	2000-06-13
Stack gate flash memory cell featuring symmetric self aligned contact structures Grant 6,037,223 - Su , et al. March 14, 2	2000-03-14
Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby Grant 6,013,551 - Chen , et al. January 11, 2	2000-01-11

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