Chen; Jau-Wen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Jau-Wen.The latest application filed is for "electrostatic discharge protection circuit having high allowable power-up slew rate".

Company Profile

0.13.13

Chen; Jau-Wen - Cupertino CA US
Chen; Jau-Wen - Milpitas CA
Chen; Jau-Wen - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Electrostatic discharge protection circuit having high allowable power-up slew rate Grant 9,172,241 - Chen October 27, 2	2015-10-27
Electrostatic Discharge Protection Circuit Having High Allowable Power-up Slew Rate App 20130258533 - CHEN; Jau-Wen	2013-10-03
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process Grant 8,269,280 - Chen September 18, 2	2012-09-18
I/O and Power ESD Protection Circuits By Enhancing Substrate-Bias in Deep-Submicron CMOS Process App 20110215410 - Chen; Jau-Wen	2011-09-08
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process Grant 7,948,036 - Chen May 24, 2	2011-05-24
Circuit protection system Grant 7,777,996 - Loh , et al. August 17, 2	2010-08-17
Design of silicon-controlled rectifier by considering electrostatic discharge robustness in human-body model and charged-device model devices Grant 7,763,908 - Chen July 27, 2	2010-07-27
I/o And Power Esd Protection Circuits By Enhancing Substrate-bias In Deep-submicron Cmos Process App 20090294856 - Chen; Jau-Wen	2009-12-03
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process Grant 7,582,938 - Chen September 1, 2	2009-09-01
Electrostatic discharge series protection Grant 7,551,414 - Loh , et al. June 23, 2	2009-06-23
Bias for electrostatic discharge protection Grant 7,379,281 - Loh , et al. May 27, 2	2008-05-27
Electrostatic discharge testing Grant 7,375,543 - Ito , et al. May 20, 2	2008-05-20
Optimization of NMOS drivers using self-ballasting ESD protection technique in fully silicided CMOS process Grant 7,317,228 - Chen January 8, 2	2008-01-08
Electrostatic discharge series protection App 20070138973 - Loh; William M. ; et al.	2007-06-21
Bias for electrostatic discharge protection App 20070121262 - Loh; William M. ; et al.	2007-05-31
Design of silicon-controlled rectifier by considering electrostatic discharge robustness in human-body model and charged-device model devices App 20070045656 - Chen; Jau-Wen	2007-03-01
Circuit protection system App 20070019345 - Loh; William M. ; et al.	2007-01-25
Electrostatic discharge testing App 20070018670 - Ito; Choshu ; et al.	2007-01-25
Implantation method to improve ESD robustness of thick gate-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies Grant 7,119,405 - Chen , et al. October 10, 2	2006-10-10
Novel implantation method to improve ESD robustness of thick gate-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies App 20060180863 - Chen; Jau-Wen ; et al.	2006-08-17
Design and optimization of NMOS drivers using self-ballasting ESD protection technique in fully salicided CMOS process App 20060175665 - Chen; Jau-Wen	2006-08-10
I/O and power ESD protection circuits by enhancing substrate-bias in deep-submicron CMOS process App 20060033163 - Chen; Jau-Wen	2006-02-16
Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process Grant 6,979,869 - Chen , et al. December 27, 2	2005-12-27
Substrate-biased I/O and power ESD protection circuits in deep-submicron twin-well process App 20050082621 - Chen, Jau-Wen ; et al.	2005-04-21

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.