Chen; Ihao

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Ihao.The latest application filed is for "method and system for providing fast design for testability prototyping in integrated circuit designs".

Company Profile

0.8.6

Chen; Ihao - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for providing fast design for testability prototyping in integrated circuit designs Grant 7,134,106 - Huang , et al. November 7, 2	2006-11-07
Timing based scan chain implementation in an IC design Grant 7,127,695 - Huang , et al. October 24, 2	2006-10-24
Automatic clock gating insertion in an IC design Grant 7,080,334 - Fan , et al. July 18, 2	2006-07-18
Method and apparatus for simulation system compiler Grant 7,080,365 - Broughton , et al. July 18, 2	2006-07-18
Method and apparatus for cycle-based computation Grant 7,036,114 - McWilliams , et al. April 25, 2	2006-04-25
Scan insertion with bypass login in an IC design Grant 6,973,631 - Huang , et al. December 6, 2	2005-12-06
Method and system for providing fast design for testability prototyping in integrated circuit designs App 20050228616 - Huang, Steve C. ; et al.	2005-10-13
Automatic clock gating insertion in an IC design App 20040225978 - Fan, Yong ; et al.	2004-11-11
Timing based scan chain implementation in an IC design App 20040015803 - Huang, Steve C. ; et al.	2004-01-22
Scan insertion with bypass login in an IC design App 20040015788 - Huang, Steve C. ; et al.	2004-01-22
Method and apparatus for simulation system compiler App 20030188299 - Broughton, Jeffrey M. ; et al.	2003-10-02
Method and apparatus for cycle-based computation App 20030040896 - McWilliams, Thomas M. ; et al.	2003-02-27
Synthesizing sequential devices from hardware description languages (HDLS) Grant 6,415,420 - Cheng , et al. July 2, 2	2002-07-02
Dynamic weighting and/or target zone analysis in timing driven placement of cells of an integrated circuit design Grant 6,415,426 - Chang , et al. July 2, 2	2002-07-02

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