Chen; Houfei

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chen; Houfei.The latest application filed is for "methods and apparatus for bi-directional control of computing unit frequency".

Company Profile

1.16.17

Chen; Houfei - Campbell CA
Chen; Houfei - Boise ID
Chen; Houfei - Seattle WA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods And Apparatus For Bi-directional Control Of Computing Unit Frequency App 20220113781 - Dai; Jianwei ; et al.	2022-04-14
Method for forming a circuit board via structure for high speed signaling Grant 9,622,358 - Zhao , et al. April 11, 2	2017-04-11
Method For Forming A Circuit Board Via Structure For High Speed Signaling App 20150250060 - Zhao; Shiyou ; et al.	2015-09-03
Method for forming a circuit board via structure for high speed signaling Grant 9,055,702 - Zhao , et al. June 9, 2	2015-06-09
Methods for suppressing power plane noise Grant 8,743,555 - Chen , et al. June 3, 2	2014-06-03
Method for Forming a Circuit Board Via Structure for High Speed Signaling App 20130340250 - Zhao; Shiyou ; et al.	2013-12-26
Methods For Suppressing Power Plane Noise App 20130326871 - Chen; Houfei ; et al.	2013-12-12
Method for forming a circuit board via structure for high speed signaling Grant 8,516,695 - Zhao , et al. August 27, 2	2013-08-27
Substrates, systems, and devices including structures for suppressing power and ground plane noise, and methods for suppressing power and ground plane noise Grant 8,508,950 - Chen , et al. August 13, 2	2013-08-13
On-die anti-resonance structure for integrated circuit Grant 8,243,479 - Chen August 14, 2	2012-08-14
On-die Anti-resonance Structure For Integrated Circuit App 20120007669 - Chen; Houfei	2012-01-12
Method for Forming a Circuit Board Via Structure for High Speed Signaling App 20110277323 - Zhao; Shiyou ; et al.	2011-11-17
On-die anti-resonance structure for integrated circuit Grant 8,023,293 - Chen September 20, 2	2011-09-20
Method for forming a circuit board via structure for high speed signaling Grant 7,992,297 - Zhao , et al. August 9, 2	2011-08-09
Substrates, Systems, And Devices Including Structures For Suppressing Power And Ground Plane Noise, And Methods For Suppressing Power And Ground Plane Noise App 20100284134 - Chen; Houfei ; et al.	2010-11-11
Substrates, systems, and devices including structures for suppressing power and ground plane noise, and methods for suppressing power and ground plane noise Grant 7,778,039 - Chen , et al. August 17, 2	2010-08-17
Method for Forming a Circuit Board Via Structure for High Speed Signaling App 20100132191 - Zhao; Shiyou ; et al.	2010-06-03
On-die Anti-resonance Structure For Integrated Circuit App 20100073972 - Chen; Houfei	2010-03-25
Method for forming a circuit board via structure for high speed signaling Grant 7,676,919 - Zhao , et al. March 16, 2	2010-03-16
S-matrix technique for circuit simulation Grant 7,660,708 - Chen February 9, 2	2010-02-09
On-die anti-resonance structure for integrated circuit Grant 7,633,773 - Chen December 15, 2	2009-12-15
Absorbing boundary for a multi-layer circuit board structure Grant 7,459,638 - Chen , et al. December 2, 2	2008-12-02
On-die Anti-resonance Structure For Integrated Circuit App 20070262794 - Chen; Houfei	2007-11-15
Substrates, systems, and devices including structures for suppressing power and ground plane noise, and methods for suppressing power and ground plane noise App 20070258173 - Chen; Houfei ; et al.	2007-11-08
Impedance matching via structure for high-speed printed circuit boards and method of determining same App 20070193775 - Chen; Houfei ; et al.	2007-08-23
S-matrix technique for circuit simulation App 20070038428 - Chen; Houfei	2007-02-15
Method for Forming a Circuit Board Via Structure for High Speed Signaling App 20070007031 - Zhao; Shiyou ; et al.	2007-01-11
Methods for modeling interactions between massively coupled multiple vias in multilayered electronic packaging structures Grant 7,149,666 - Tsang , et al. December 12, 2	2006-12-12
Absorbing boundary for a multi-layer circuit board structure App 20060237223 - Chen; Houfei ; et al.	2006-10-26
Circuit board via structure for high speed signaling App 20060237227 - Zhao; Shiyou ; et al.	2006-10-26
Methods for modeling interactions between massively coupled multiple vias in multilayered electronic packaging structures App 20030072130 - Tsang, Leung ; et al.	2003-04-17

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