Chelstrom; Nathan P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chelstrom; Nathan P..The latest application filed is for "controlling asynchronous clock domains to perform synchronous operations".

Company Profile

0.10.11

Chelstrom; Nathan P. - Cedar Park TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Controlling asynchronous clock domains to perform synchronous operations Grant 8,144,689 - Chelstrom , et al. March 27, 2	2012-03-27
Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device Grant 7,908,536 - Chelstrom , et al. March 15, 2	2011-03-15
Method and apparatus for testing a ring of non-scan latches with logic built-in self-test Grant 7,797,600 - Bushard , et al. September 14, 2	2010-09-14
Controlling asynchronous clock domains to perform synchronous operations Grant 7,792,154 - Chelstrom , et al. September 7, 2	2010-09-07
Using eFuses to store PLL configuration data Grant 7,688,930 - Beattie , et al. March 30, 2	2010-03-30
Clock control hierarchy for integrated microprocessors and systems-on-a-chip Grant 7,627,771 - Chelstrom , et al. December 1, 2	2009-12-01
Apparatus and method for using eFuses to store PLL configuration data Grant 7,562,272 - Beattie , et al. July 14, 2	2009-07-14
Controlling Asynchronous Clock Domains to Perform Synchronous Operations App 20090106575 - Chelstrom; Nathan P. ; et al.	2009-04-23
Testing Functional Boundary Logic at Asynchronous Clock Boundaries of an Integrated Circuit Device App 20090083594 - Chelstrom; Nathan P. ; et al.	2009-03-26
Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologies Grant 7,500,164 - Chelstrom , et al. March 3, 2	2009-03-03
Method for controlling asynchronous clock domains to perform synchronous operations Grant 7,492,793 - Chelstrom , et al. February 17, 2	2009-02-17
Method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device Grant 7,478,300 - Chelstrom , et al. January 13, 2	2009-01-13
Using eFuses to Store PLL Configuration Data App 20080225566 - Beattie; Irene ; et al.	2008-09-18
Controlling Asynchronous Clock Domains to Perform Synchronous Operations App 20080229136 - Chelstrom; Nathan P. ; et al.	2008-09-18
System And Method For Testing An Integrated Circuit Device Having Elements With Asynchronous Clocks Or Dissimilar Design Methodologies App 20070283205 - Chelstrom; Nathan P. ; et al.	2007-12-06
System And Method For Testing Functional Boundary Logic At Asynchronous Clock Boundaries Of An Integrated Circuit Device App 20070266284 - Chelstrom; Nathan P. ; et al.	2007-11-15
Method and apparatus for processing error information and injecting errors in a processor system App 20070174679 - Chelstrom; Nathan P. ; et al.	2007-07-26
Clock control hierarchy for integrated microprocessors and systems-on-a-chip App 20070168688 - Chelstrom; Nathan P. ; et al.	2007-07-19
RUNN counter phase control App 20070092048 - Chelstrom; Nathan P. ; et al.	2007-04-26
Apparatus and method for controlling asynchronous clock domains to perform synchronous operations App 20070091933 - Chelstrom; Nathan P. ; et al.	2007-04-26
Apparatus and method for using eFuses to store PLL configuration data App 20070081620 - Beattie; Irene ; et al.	2007-04-12

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