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Patent applications and USPTO patent grants for Chebiam; Ramanan.The latest application filed is for "subtractively patterned interconnect structures for integrated circuits".
Patent | Date |
---|---|
Subtractively patterned interconnect structures for integrated circuits Grant 11,444,024 - Lin , et al. September 13, 2 | 2022-09-13 |
Interconnect structures and methods of fabrication Grant 11,404,307 - Chandhok , et al. August 2, 2 | 2022-08-02 |
Subtractively Patterned Interconnect Structures For Integrated Circuits App 20220139823 - Lin; Kevin ;   et al. | 2022-05-05 |
Metallization Barrier Structures For Bonded Integrated Circuit Interfaces App 20210098387 - Naylor; Carl ;   et al. | 2021-04-01 |
Nterconnect Structures And Methods Of Fabrication App 20210098360 - Chandhok; Manish ;   et al. | 2021-04-01 |
Scalable interconnect structures with selective via posts Grant 9,391,019 - Kobrinsky , et al. July 12, 2 | 2016-07-12 |
Scalable Interconnect Structures With Selective Via Posts App 20150270211 - Kobrinsky; Mauro ;   et al. | 2015-09-24 |
Selective Electroless Metal Deposition For Dual Salicide Process App 20090315185 - Boyanov; Boyan ;   et al. | 2009-12-24 |
Metal Interconnect Structures For Semiconductor Devices App 20090166867 - Simka; Harsono ;   et al. | 2009-07-02 |
Treating a liner layer to reduce surface oxides Grant 7,470,617 - Chebiam , et al. December 30, 2 | 2008-12-30 |
Treating a liner layer to reduce surface oxides App 20080213994 - Chebiam; Ramanan ;   et al. | 2008-09-04 |
Method of forming metal on a substrate using a Ruthenium-based catalyst App 20070004587 - Chebiam; Ramanan ;   et al. | 2007-01-04 |
Methods for bonding wafers using a metal interlayer App 20040262772 - Ramanathan, Shriram ;   et al. | 2004-12-30 |
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