loadpatents
name:-0.03580117225647
name:-0.014073133468628
name:-0.0071640014648438
CHAWLA; Nitin Patent Filings

CHAWLA; Nitin

Patent Applications and Registrations

Patent applications and USPTO patent grants for CHAWLA; Nitin.The latest application filed is for "tagged memory operated at lower vmin in error tolerant system".

Company Profile
4.13.19
  • CHAWLA; Nitin - Noida IN
  • CHAWLA; Nitin - New Delhi IN
  • Chawla; Nitin - Noida U.P.
  • Chawla; Nitin - Up IN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Tagged Memory Operated At Lower Vmin In Error Tolerant System
App 20220269410 - CHAWLA; Nitin ;   et al.
2022-08-25
Tagged memory operated at lower vmin in error tolerant system
Grant 11,360,667 - Chawla , et al. June 14, 2
2022-06-14
Memory Management Device, System And Method
App 20220139453 - CHAWLA; Nitin ;   et al.
2022-05-05
Memory management device, system and method
Grant 11,257,543 - Chawla , et al. February 22, 2
2022-02-22
In-memory Compute Array With Integrated Bias Elements
App 20210343334 - GROVER; Anuj ;   et al.
2021-11-04
In-memory compute array with integrated bias elements
Grant 11,094,376 - Grover , et al. August 17, 2
2021-08-17
Streaming Access Memory Device, System And Method
App 20210241806 - CHAWLA; Nitin ;   et al.
2021-08-05
Computing System Power Management Device, System And Method
App 20210181828 - CHAWLA; Nitin ;   et al.
2021-06-17
Variable Clock Adaptation In Neural Network Processors
App 20210081773 - CHAWLA; Nitin ;   et al.
2021-03-18
Tagged Memory Operated At Lower Vmin In Error Tolerant System
App 20210072894 - CHAWLA; Nitin ;   et al.
2021-03-11
Memory Management Device, System And Method
App 20200411089 - CHAWLA; Nitin ;   et al.
2020-12-31
In-memory Compute Array With Integrated Bias Elements
App 20200388330 - GROVER; Anuj ;   et al.
2020-12-10
Elements For In-memory Compute
App 20200387352 - CHAWLA; Nitin ;   et al.
2020-12-10
Deep Convolutional Network Heterogeneous Architecture
App 20180189229 - DESOLI; Giuseppe ;   et al.
2018-07-05
Calibration arrangement
Grant 9,021,324 - Chawla , et al. April 28, 2
2015-04-28
Adaptive multi-stage slack borrowing for high performance error resilient computing
Grant 8,994,416 - Parthasarathy , et al. March 31, 2
2015-03-31
Adaptive Multi-stage Slack Borrowing For High Performance Error Resilient Computing
App 20140035644 - PARTHASARATHY; Chittoor ;   et al.
2014-02-06
Adaptive multi-stage slack borrowing for high performance error resilient computing
Grant 8,552,765 - Parthasarathy , et al. October 8, 2
2013-10-08
Fail safe adaptive voltage/frequency system
Grant 8,269,545 - Chawla , et al. September 18, 2
2012-09-18
Adaptive Multi-stage Slack Borrowing For High Performance Error Resilient Computing
App 20120176173 - PARTHASARATHY; Chittoor ;   et al.
2012-07-12
Calibration Arrangement
App 20120158339 - Chawla; Nitin ;   et al.
2012-06-21
Fail safe adaptive voltage/frequency system
Grant 8,154,335 - Chawla , et al. April 10, 2
2012-04-10
Fail Safe Adaptive Voltage/frequency System
App 20120044005 - Chawla; Nitin ;   et al.
2012-02-23
Spread spectrum clock generation
Grant 8,037,336 - Chawla October 11, 2
2011-10-11
Device for implementing a sum of products expression
Grant 7,917,569 - Bhuvanagiri , et al. March 29, 2
2011-03-29
Fail Safe Adaptive Voltage/frequency System
App 20110068858 - Chawla; Nitin ;   et al.
2011-03-24
Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry
Grant 7,698,355 - Bhuvanagiri , et al. April 13, 2
2010-04-13
Spread spectrum clock generation
App 20080129351 - Chawla; Nitin
2008-06-05
Device for implementing a sum of products expression
App 20060153321 - Bhuvanagiri; Aditya ;   et al.
2006-07-13
Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry
App 20060120494 - Bhuvanagiri; Aditya ;   et al.
2006-06-08

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