loadpatents
name:-0.011415004730225
name:-0.022119998931885
name:-0.0032048225402832
Chaware; Raghunandan Patent Filings

Chaware; Raghunandan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chaware; Raghunandan.The latest application filed is for "die singulation and stacked device structures".

Company Profile
2.26.11
  • Chaware; Raghunandan - Sunnyvale CA
  • Chaware; Raghunandan - Mountain View CA
  • CHAWARE; Raghunandan - Fremont CA
  • Chaware; Raghunandan - Huntington Beach CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Die singulation and stacked device structures
Grant 11,075,117 - Hariharan , et al. July 27, 2
2021-07-27
Stacked silicon package assembly having enhanced stiffener
Grant 10,840,192 - Zohni , et al. November 17, 2
2020-11-17
Die Singulation And Stacked Device Structures
App 20190267287 - Hariharan; Ganesh ;   et al.
2019-08-29
Temporary connection traces for wafer sort testing
Grant 10,204,841 - Klein , et al. Feb
2019-02-12
Multi-die wafer-level test and assembly without comprehensive individual die singulation
Grant 10,032,682 - Klein , et al. July 24, 2
2018-07-24
Method and apparatus for testing interposer dies prior to assembly
Grant 9,989,572 - Chaware , et al. June 5, 2
2018-06-05
Heterogeneous integration of integrated circuit device and companion device
Grant 9,865,567 - Chaware , et al. January 9, 2
2018-01-09
Interposer-less stack die interconnect
Grant 9,761,533 - Chaware , et al. September 12, 2
2017-09-12
Interposer-less Stack Die Interconnect
App 20170110407 - Chaware; Raghunandan ;   et al.
2017-04-20
Stacked silicon package assembly having enhanced lid adhesion
Grant 9,418,909 - Chaware , et al. August 16, 2
2016-08-16
Method for providing charge protection to one or more dies during formation of a stacked silicon device
Grant 9,385,106 - Chaware , et al. July 5, 2
2016-07-05
Integrated circuit package testing
Grant 9,341,668 - Hariharan , et al. May 17, 2
2016-05-17
Method for removing bumps from incomplete and defective interposer dies for stacked silicon interconnect technology (SSIT) devices
Grant 8,900,987 - Singh , et al. December 2, 2
2014-12-02
System And Method For Laminating Photovoltaic Structures
App 20140312530 - MAHESHWARI; Abhay ;   et al.
2014-10-23
Semiconductor structure and method for interconnection of integrated circuits
Grant 8,841,752 - Chaware , et al. September 23, 2
2014-09-23
System and method for laminating photovoltaic structures
Grant 8,766,086 - Maheshwari , et al. July 1, 2
2014-07-01
Stacked die assembly
Grant 8,704,384 - Wu , et al. April 22, 2
2014-04-22
Semiconductor structure and method for interconnection of integrated circuits
Grant 8,519,528 - Nagarajan , et al. August 27, 2
2013-08-27
Stacked Die Assembly
App 20130214432 - Wu; Ephrem C. ;   et al.
2013-08-22
System And Method For Determining Placement Of Photovoltaic Strips Using Displacement Sensors
App 20130206208 - SHAH; Shirish ;   et al.
2013-08-15
Apparatus and methodology for testing stacked die
Grant 8,415,783 - Rahman , et al. April 9, 2
2013-04-09
System and method for determining placement of photovoltaic strips using displacement sensors
Grant 8,361,259 - Shah , et al. January 29, 2
2013-01-29
Photovoltaic Strip Solar Modules And Methods
App 20120211052 - MARATHE; Ajay ;   et al.
2012-08-23
System And Method For Forming Photovoltaic Modules
App 20120167948 - Marathe; Ajay ;   et al.
2012-07-05
System And Method For Laminating Photovoltaic Structures
App 20120067398 - MAHESHWARI; Abhay ;   et al.
2012-03-22
System And Method For Determining Placement Of Photovoltaic Strips Using Displacement Sensors
App 20120067397 - Shah; Shirish ;   et al.
2012-03-22
Molded integrated circuit package and method of forming a molded integrated circuit package
Grant 7,906,857 - Hoang , et al. March 15, 2
2011-03-15
Low cost bumping and bonding method for stacked die
Grant 7,863,092 - Chaware , et al. January 4, 2
2011-01-04
Process for exposing solder bumps on an underfill coated semiconductor
Grant 7,338,842 - Chaware , et al. March 4, 2
2008-03-04
Process for exposing solder bumps on an underfill coated semiconductor
App 20070020815 - Chaware; Raghunandan ;   et al.
2007-01-25

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