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name:-0.021075010299683
name:-0.01920485496521
Chavali; Sri Chaitra Jyotsna Patent Filings

Chavali; Sri Chaitra Jyotsna

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chavali; Sri Chaitra Jyotsna.The latest application filed is for "coreless electronic substrates having embedded inductors".

Company Profile
21.14.27
  • Chavali; Sri Chaitra Jyotsna - Chandler AZ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Coreless Electronic Substrates Having Embedded Inductors
App 20220293327 - Ganesan; Sanka ;   et al.
2022-09-15
Antenna Package Using Ball Attach Array To Connect Antenna And Base Substrates
App 20220216611 - Yao; Jimin ;   et al.
2022-07-07
Selectively Roughened Copper Architectures For Low Insertion Loss Conductive Features
App 20220102259 - Kong; Jieying ;   et al.
2022-03-31
High density package substrate formed with dielectric bi-layer
Grant 11,276,634 - Pietambaram , et al. March 15, 2
2022-03-15
High Density Organic Interconnect Structures
App 20220059367 - Chavali; Sri Chaitra Jyotsna ;   et al.
2022-02-24
High density organic interconnect structures
Grant 11,195,727 - Chavali , et al. December 7, 2
2021-12-07
Integrated Circuit Structures In Package Substrates
App 20210351116 - Ganesan; Sanka ;   et al.
2021-11-11
Integrated circuit structures in package substrates
Grant 11,107,757 - Ganesan , et al. August 31, 2
2021-08-31
Microelectronic Device Including Fiber-containing Build-up Layers
App 20210242132 - Chavali; Sri Chaitra Jyotsna
2021-08-05
Embedded Die Architecture And Method Of Making
App 20210193579 - Ganesan; Sanka ;   et al.
2021-06-24
Microelectronic device including fiber-containing build-up layers
Grant 11,004,792 - Chavali May 11, 2
2021-05-11
Hybrid Core Substrate Architecture For High Speed Signaling And Fli/sli Reliability And Its Making
App 20210125932 - CHAVALI; Sri Chaitra Jyotsna
2021-04-29
Package Embedded Magnetic Inductor Structures And Manufacturing Techniques For 5-50 Mhz Smps Operations
App 20210125944 - LAMBERT; William J. ;   et al.
2021-04-29
Asymmetric electronic substrate and method of manufacture
Grant 10,980,129 - Chavali , et al. April 13, 2
2021-04-13
Scalable High Speed High Bandwidth Io Signaling Package Architecture And Method Of Making
App 20210028116 - GANESAN; Sanka ;   et al.
2021-01-28
Electrical interconnections with improved compliance due to stress relaxation and method of making
Grant 10,903,137 - Alur , et al. January 26, 2
2021-01-26
Inductors For Package Substrates
App 20210005550 - CHAVALI; Sri Chaitra Jyotsna ;   et al.
2021-01-07
High Density Organic Interconnect Structures
App 20200312675 - Chavali; Sri Chaitra Jyotsna ;   et al.
2020-10-01
Integrated Circuit Structures In Package Substrates
App 20200251411 - Kind Code
2020-08-06
Asymmetric Electronic Substrate And Method Of Manufacture
App 20200221577 - Chavali; Sri Chaitra Jyotsna ;   et al.
2020-07-09
High density organic interconnect structures
Grant 10,685,850 - Chavali , et al.
2020-06-16
Integrated circuit structures in package substrates
Grant 10,672,693 - Ganesan , et al.
2020-06-02
Edge-firing antenna walls built into substrate
Grant 10,658,765 - Chavali , et al.
2020-05-19
Asymmetric electronic substrate and method of manufacture
Grant 10,624,213 - Chavali , et al.
2020-04-14
Microelectronic Device Including Fiber-containing Build-up Layers
App 20200105674 - Chavali; Sri Chaitra Jyotsna
2020-04-02
Stacked Wire-bond Dice Attached By Pillars Or Bumps Above A Flip-chip Die On A Semiconductor Package Substrate
App 20200098727 - Mallik; Debendra ;   et al.
2020-03-26
High Density Package Substrate Formed With Dielectric Bi-layer
App 20200075473 - Pietambaram; Srinivas V. ;   et al.
2020-03-05
Edge-firing Antenna Walls Built Into Substrate
App 20200006866 - Chavali; Sri Chaitra Jyotsna ;   et al.
2020-01-02
Microelectronic Device Interconnect Structure
App 20200006273 - Dubey; Manish ;   et al.
2020-01-02
Electrical Interconnections With Improved Compliance Due To Stress Relaxation And Method Of Making
App 20190393129 - Alur; Siddharth K. ;   et al.
2019-12-26
Integrated Circuit Structures In Package Substrates
App 20190304887 - Ganesan; Sanka ;   et al.
2019-10-03
Electrical interconnections with improved compliance due to stress relaxation and method of making
Grant 10,424,530 - Alur , et al. Sept
2019-09-24
Integrated circuit structures with recessed conductive contacts for package on package
Grant 10,424,561 - Lee , et al. Sept
2019-09-24
High Density Organic Interconnect Structures
App 20190221447 - Chavali; Sri Chaitra Jyotsna ;   et al.
2019-07-18
Integrated Circuit Structures With Recessed Conductive Contacts For Package On Package
App 20180226381 - LEE; KYU-OH ;   et al.
2018-08-09
Metal protected fan-out cavity
Grant 9,953,959 - Darmawikarta , et al. April 24, 2
2018-04-24
Integrated circuit structures with recessed conductive contacts for package on package
Grant 9,865,568 - Lee , et al. January 9, 2
2018-01-09
Integrated Circuit Structures With Recessed Conductive Contacts For Package On Package
App 20170207196 - LEE; KYU-OH ;   et al.
2017-07-20

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