Chauhan; Vikrant

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chauhan; Vikrant.The latest application filed is for "test structures connected with the lowest metallization levels in an interconnect structure".

Company Profile

8.12.13

Chauhan; Vikrant - Cohoes NY
Chauhan; Vikrant - Clifton Park NY
Chauhan; Vikrant - Beacon NY
Chauhan; Vikrant - Ossining NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Test structures connected with the lowest metallization levels in an interconnect structure Grant 10,796,973 - Yang , et al. October 6, 2	2020-10-06
Test structure leveraging the lowest metallization level of an interconnect structure Grant 10,790,204 - Yang , et al. September 29, 2	2020-09-29
Test Structure Leveraging The Lowest Metallization Level Of An Interconnect Structure App 20200152530 - Yang; Mankyu ; et al.	2020-05-14
Test Structures Connected With The Lowest Metallization Levels In An Interconnect Structure App 20200152531 - Yang; Mankyu ; et al.	2020-05-14
FDSOI semiconductor device with contact enhancement layer and method of manufacturing Grant 10,347,543 - Baars , et al. July 9, 2	2019-07-09
Three-dimensional pattern risk scoring Grant 10,311,186 - Bravo , et al.	2019-06-04
Fdsoi Semiconductor Device With Contact Enhancement Layer And Method Of Manufacturing App 20190148245 - Baars; Peter ; et al.	2019-05-16
Multi-directional self-aligned multiple patterning Grant 10,199,270 - Bombardier , et al. Fe	2019-02-05
On-chip capacitors with floating islands Grant 10,147,783 - Ogino , et al. De	2018-12-04
Multi-directional Self-aligned Multiple Patterning App 20180342421 - Bombardier; Colin ; et al.	2018-11-29
On-chip Capacitors With Floating Islands App 20180269275 - Ogino; Atsushi ; et al.	2018-09-20
Wafer level electrical test for optical proximity correction and/or etch bias Grant 10,078,107 - Bravo , et al. September 18, 2	2018-09-18
Method For Forming A Shallow Trench Isolation Structure Using A Nitride Liner And A Diffusionless Anneal App 20180040505 - Gaan; Sandeep ; et al.	2018-02-08
Three-dimensional Pattern Risk Scoring App 20170293704 - BRAVO; Jaime ; et al.	2017-10-12
Wafer Level Electrical Test For Optical Proximity Correction And/or Etch Bias App 20170115337 - BRAVO; Jaime ; et al.	2017-04-27
Multi-polygon constraint decomposition techniques for use in double patterning applications Grant 9,465,907 - Hassan , et al. October 11, 2	2016-10-11
Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines Grant 9,412,655 - Bouche , et al. August 9, 2	2016-08-09
Forming Merged Lines In A Metallization Layer By Replacing Sacrificial Lines With Conductive Lines App 20160225666 - Bouche; Guillaume ; et al.	2016-08-04
Multi-polygon Constraint Decomposition Techniques For Use In Double Patterning Applications App 20160026748 - Hassan; Ahmed ; et al.	2016-01-28
Critical Dimension And Pattern Recognition Structures For Devices Manufactured Using Double Patterning Techniques App 20150050811 - Mehta; Sohan ; et al.	2015-02-19
Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques Grant 8,932,961 - Mehta , et al. January 13, 2	2015-01-13
Capacitor designs for integrated circuits utilizing self-aligned double patterning (SADP) Grant 8,856,715 - Stephens , et al. October 7, 2	2014-10-07
Critical Dimension and Pattern Recognition Structures for Devices Manufactured Using Double Patterning Techniques App 20130207108 - Mehta; Sohan ; et al.	2013-08-15

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