Chaudhary; Kamal

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chaudhary; Kamal.The latest application filed is for "one phase logic".

Company Profile

0.31.5

Chaudhary; Kamal - Saratoga CA
Chaudhary; Kamal - San Jose CA
Chaudhary; Kamal - Milpitas CA
Chaudhary; Kamal - Berkeley CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
One phase logic Grant 8,593,176 - Nijssen , et al. November 26, 2	2013-11-26
Non-predicated to predicated conversion of asynchronous representations Grant 8,191,019 - Manohar , et al. May 29, 2	2012-05-29
One Phase Logic App 20120112792 - Nijssen; Raymond ; et al.	2012-05-10
Latch based optimization during implementation of circuit designs for programmable logic devices Grant 8,146,041 - Srinivasan , et al. March 27, 2	2012-03-27
One phase logic Grant 8,106,683 - Nijssen , et al. January 31, 2	2012-01-31
One Phase Logic App 20110298495 - Nijssen; Raymond ; et al.	2011-12-08
Latch based optimization during implementation of circuit designs for programmable logic devices Grant 8,010,923 - Srinivasan , et al. August 30, 2	2011-08-30
One phase logic Grant 7,932,746 - Nijssen , et al. April 26, 2	2011-04-26
Non-predicated To Predicated Conversion Of Asynchronous Representations App 20110012666 - Manohar; Rajit ; et al.	2011-01-20
Fanout-optimization during physical synthesis for placed circuit designs Grant 7,853,914 - Srinivasan , et al. December 14, 2	2010-12-14
Placing partitioned circuit designs within iterative implementation flows Grant 7,590,960 - Kong , et al. September 15, 2	2009-09-15
Incremental placement during physical synthesis Grant 7,536,661 - Singh , et al. May 19, 2	2009-05-19
Enhanced incremental placement during physical synthesis Grant 7,428,718 - Singh , et al. September 23, 2	2008-09-23
Congestion estimation for programmable logic devices Grant 7,146,590 - Chaudhary December 5, 2	2006-12-05
Circuits and methods for testing programmable logic devices using lookup tables and carry chains Grant 7,111,214 - Chaudhary , et al. September 19, 2	2006-09-19
Programmable circuit optionally configurable as a lookup table or a wide multiplexer Grant 7,075,333 - Chaudhary , et al. July 11, 2	2006-07-11
Relocation of components for post-placement optimization Grant 7,072,815 - Chaudhary , et al. July 4, 2	2006-07-04
Pin reordering during placement of circuit designs Grant 7,058,915 - Singh , et al. June 6, 2	2006-06-06
Interconnect structure for a programmable logic device Grant 6,448,808 - Young , et al. September 10, 2	2002-09-10
Method for analytical placement of cells using density surface representations Grant 6,415,425 - Chaudhary , et al. July 2, 2	2002-07-02
Multiplexer for implementing logic functions in a programmable logic device Grant 6,362,648 - New , et al. March 26, 2	2002-03-26
Interconnect structure for a programmable logic device App 20020008541 - Young, Steven P. ; et al.	2002-01-24
Delay optimized mapping for programmable gate arrays with multiple sized lookup tables Grant 6,336,208 - Mohan , et al. January 1, 2	2002-01-01
Interconnect structure for a programmable logic device App 20010007428 - Young, Steven P. ; et al.	2001-07-12
Wide logic gate implemented in an FPGA configurable logic element Grant 6,201,410 - New , et al. March 13, 2	2001-03-13
Configurable logic element with ability to evaluate wide logic functions Grant 6,124,731 - Young , et al. September 26, 2	2000-09-26
FPGA CLE with two independent carry chains Grant 6,107,827 - Young , et al. August 22, 2	2000-08-22
Post-placement residual overlap removal method for core-based PLD programming process Grant 6,086,631 - Chaudhary , et al. July 11, 2	2000-07-11
Configurable logic element with ability to evaluate five and six input functions Grant 6,051,992 - Young , et al. April 18, 2	2000-04-18
Configurable logic element with fast feedback paths Grant 5,963,050 - Young , et al. October 5, 1	1999-10-05
High speed bus with tree structure for selecting bus driver Grant 5,936,424 - Young , et al. August 10, 1	1999-08-10
FPGA repeatable interconnect structure with hierarchical interconnect lines Grant 5,914,616 - Young , et al. June 22, 1	1999-06-22
FPGA having logic element carry chains capable of generating wide XOR functions Grant 5,889,411 - Chaudhary March 30, 1	1999-03-30
High speed tristate bus with multiplexers for selecting bus driver Grant 5,677,638 - Young , et al. October 14, 1	1997-10-14
Field programmable logic device with dynamic interconnections to a dynamic logic core Grant 5,596,743 - Bhat , et al. January 21, 1	1997-01-21

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