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Patent applications and USPTO patent grants for Chau; Pak S..The latest application filed is for "multi-pam output driver with distortion compensation".
Patent | Date |
---|---|
Multi-PAM output driver with distortion compensation Grant 9,998,305 - Zerbe , et al. June 12, 2 | 2018-06-12 |
Multi-PAM Output Driver with Distortion Compensation App 20170222845 - Zerbe; Jared L. ;   et al. | 2017-08-03 |
Integrated circuit comprising a delay-locked loop Grant 9,160,350 - Zerbe , et al. October 13, 2 | 2015-10-13 |
Multiphase Receiver with Equalization Circuitry App 20140286389 - Zerbe; Jared L. ;   et al. | 2014-09-25 |
Multiphase receiver with equalization circuitry Grant 8,634,452 - Zerbe , et al. January 21, 2 | 2014-01-21 |
Integrated Circuit Comprising A Delay-locked Loop App 20130121094 - Zerbe; Jared L. ;   et al. | 2013-05-16 |
Multiphase receiver with equalization circuitry App 20130010855 - Zerbe; Jared L. ;   et al. | 2013-01-10 |
Integrating receiver with precharge circuitry Grant 8,199,859 - Zerbe , et al. June 12, 2 | 2012-06-12 |
Integrating Receiver With Precharge Circuitry App 20110140741 - Zerbe; Jared L. ;   et al. | 2011-06-16 |
Multiphase receiver with equalization Grant 7,809,088 - Zerbe , et al. October 5, 2 | 2010-10-05 |
Low Latency Multi-Level Communication Interface App 20100134153 - Zerbe; Jared L. ;   et al. | 2010-06-03 |
Low latency multi-level communication interface Grant 7,626,442 - Zerbe , et al. December 1, 2 | 2009-12-01 |
Low latency multi-level communication interface Grant 7,124,221 - Zerbe , et al. October 17, 2 | 2006-10-17 |
Low latency multi-level communication interface App 20060170453 - Zerbe; Jared L. ;   et al. | 2006-08-03 |
Input/output circuit with on-chip inductor to reduce parasitic capacitance Grant 7,005,939 - Zerbe , et al. February 28, 2 | 2006-02-28 |
Input/output circuit with on-chip inductor to reduce parasitic capacitance App 20040155675 - Zerbe, Jared L. ;   et al. | 2004-08-12 |
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