Chatterjee; Siddhartha

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chatterjee; Siddhartha.The latest application filed is for "method for improving performance of executable code".

Company Profile

0.8.9

Chatterjee; Siddhartha - Yorktown Heights NY
Chatterjee; Siddhartha - Sunnyvale CA
Chatterjee; Siddhartha - Chapel Hill NC

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Vector unit in a processor enabled to replicate data on a first portion of a data bus to primary and secondary registers Grant 8,200,945 - Chatterjee , et al. June 12, 2	2012-06-12
Method and structure for skewed block-cyclic distribution of lower-dimensional data arrays in higher-dimensional processor grids Grant 8,055,878 - Chatterjee , et al. November 8, 2	2011-11-08
Method for improving performance of executable code Grant 7,954,094 - Cascaval , et al. May 31, 2	2011-05-31
System and method for encoding and decoding architecture registers Grant 7,596,680 - Cascaval , et al. September 29, 2	2009-09-29
Method and structure for an improved data reformatting procedure Grant 7,555,604 - Chatterjee , et al. June 30, 2	2009-06-30
Scalable runtime system for global address space languages on shared and distributed memory machines Grant 7,380,086 - Archambault , et al. May 27, 2	2008-05-27
Method for improving performance of executable code App 20070226698 - Cascaval; Gheorghe ; et al.	2007-09-27
Method and structure for an improved data reformatting procedure App 20070162703 - Chatterjee; Siddhartha ; et al.	2007-07-12
Method and structure for skewed block-cyclic distribution of lower-dimensional data arrays in higher-dimensional processor grids App 20060179267 - Chatterjee; Siddhartha ; et al.	2006-08-10
System and method for algorithmic cache-bypass App 20060179240 - Chatterjee; Siddhartha ; et al.	2006-08-10
Method and structure for high-performance linear algebra in the presence of limited outstanding miss slots App 20060168401 - Chatterjee; Siddhartha ; et al.	2006-07-27
Method and structure for algorithmic overlap in parallel processing for exploitation when load imbalance is dynamic and predictable App 20060167836 - Chatterjee; Siddhartha ; et al.	2006-07-27
Scalable runtime system for global address space languages on shared and distributed memory machines App 20050149903 - Archambault, Roch ; et al.	2005-07-07
Vector processor with data swap and replication App 20050102487 - Chatterjee, Siddhartha ; et al.	2005-05-12
System and method for encoding and decoding architecture registers App 20050060520 - Cascaval, Gheorghe C. ; et al.	2005-03-17
Method of compilation optimization using an N-dimensional template for relocated and replicated alignment of arrays in data-parallel programs for reduced data communication during execution Grant 5,475,842 - Gilbert , et al. December 12, 1	1995-12-12
Generating local addresses and communication sets for data-parallel programs Grant 5,450,313 - Gilbert , et al. September 12, 1	1995-09-12

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.