Chatterjee; Mitrajit

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chatterjee; Mitrajit.The latest application filed is for "method to dynamically inject errors in a repairable memory on silicon and a method to validate built-in-self-repair logic".

Company Profile

0.6.3

Chatterjee; Mitrajit - Santa Clara CA
Chatterjee; Mitrajit - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method to dynamically inject errors in a repairable memory on silicon and a method to validate built-in-self-repair logic Grant 10,204,698 - Kraipak , et al. Feb	2019-02-12
Method To Dynamically Inject Errors In A Repairable Memory On Silicon And A Method To Validate Built-in-self-repair Logic App 20180174665 - Kraipak; Waseem ; et al.	2018-06-21
Integrated circuit module time delay budgeting Grant 8,397,197 - Chatterjee , et al. March 12, 2	2013-03-12
Scheduler for a multiprocessing computing system Grant 7,827,555 - Chatterjee , et al. November 2, 2	2010-11-02
Memory unit with controller managing memory access through JTAG and CPU interfaces Grant 7,386,774 - Chatterjee , et al. June 10, 2	2008-06-10
Method of locating packet for resend from retry buffer App 20080072113 - Tsang; Siukwin ; et al.	2008-03-20
Scheduler for a multiprocessing computing system App 20060059487 - Chatterjee; Mitrajit ; et al.	2006-03-16
Apparatus and method for transferring multi-byte words in a fly-by DMA operation Grant 6,865,638 - Chatterjee March 8, 2	2005-03-08

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