Chatterjee; Amitava

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chatterjee; Amitava.The latest application filed is for "esd protection circuit with isolated scr for negative voltage operation".

Company Profile

1.94.76

Chatterjee; Amitava - Plano TX
Chatterjee; Amitava - Richardson TX
Chatterjee; Amitava - Garland TX
Chatterjee; Amitava - Dallas TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Esd Protection Circuit With Isolated Scr For Negative Voltage Operation App 20220189946 - Salman; Akram A. ; et al.	2022-06-16
ESD protection circuit with isolated SCR for negative voltage operation Grant 11,302,688 - Salman , et al. April 12, 2	2022-04-12
ESD protection circuit with isolated SCR for negative voltage operation Grant 11,049,852 - Salman , et al. June 29, 2	2021-06-29
I-shaped gate electrode for improved sub-threshold MOSFET performance Grant 10,608,110 - Chatterjee	2020-03-31
Esd Protection Circuit With Isolated Scr For Negative Voltage Operation App 20180350794 - Salman; Akram A. ; et al.	2018-12-06
Esd Protection Circuit With Isolated Scr For Negative Voltage Operation App 20180350795 - Salman; Akram A. ; et al.	2018-12-06
Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells Grant 10,128,145 - Benaissa , et al. November 13, 2	2018-11-13
ESD protection circuit with isolated SCR for negative voltage operation Grant 10,083,951 - Salman , et al. September 25, 2	2018-09-25
Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure Grant 9,865,507 - Hao , et al. January 9, 2	2018-01-09
I-shaped Gate Electrode For Improved Sub-threshold Mosfet Performance App 20170345929 - Chatterjee; Amitava	2017-11-30
I-shaped gate electrode for improved sub-threshold MOSFET performance Grant 9,768,296 - Chatterjee September 19, 2	2017-09-19
High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit Grant 9,721,849 - Robinson , et al. August 1, 2	2017-08-01
Drain extended CMOS with counter-doped drain extension Grant 9,583,596 - Steinmann , et al. February 28, 2	2017-02-28
Low cost demos transistor with improved CHC immunity Grant 9,577,094 - Tang , et al. February 21, 2	2017-02-21
High Performance Isolated Vertical Bipolar Junction Transistor And Method For Forming In A Cmos Integrated Circuit App 20160372376 - ROBINSON; Derek W. ; et al.	2016-12-22
Low-cost Cmos Structure With Dual Gate Dielectrics And Method Of Forming The Cmos Structure App 20160322263 - Hao; Pinghai ; et al.	2016-11-03
High performance isolated vertical bipolar junction transistor and method for forming in a CMOS integrated circuit Grant 9,461,035 - Robinson , et al. October 4, 2	2016-10-04
Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure Grant 9,431,302 - Hao , et al. August 30, 2	2016-08-30
Deep collector vertical bipolar transistor with enhanced gain Grant 9,397,164 - Hornung , et al. July 19, 2	2016-07-19
Drain Extended CMOS with Counter-Doped Drain Extension App 20160079392 - Steinmann; Philipp ; et al.	2016-03-17
Deep Collector Vertical Bipolar Transistor With Enhanced Gain App 20160079364 - Hornung; Brian E. ; et al.	2016-03-17
Low Cost Demos Transistor With Improved Chc Immunity App 20160035890 - TANG; Shaoping ; et al.	2016-02-04
Deep collector vertical bipolar transistor with enhanced gain Grant 9,245,755 - Hornung , et al. January 26, 2	2016-01-26
Drain extended CMOS with counter-doped drain extension Grant 9,231,054 - Steinmann , et al. January 5, 2	2016-01-05
I-shaped Gate Electrode For Improved Sub-threshold Mosfet Performance App 20150380551 - Chatterjee; Amitava	2015-12-31
Low cost demos transistor with improved CHC immunity Grant 9,202,912 - Tang , et al. December 1, 2	2015-12-01
Esd Protection Circuit With Isolated Scr For Negative Voltage Operation App 20150294967 - Salman; Akram A. ; et al.	2015-10-15
Low-cost Cmos Structure With Dual Gate Dielectrics And Method Of Forming The Cmos Structure App 20150249040 - Hao; Pinghai ; et al.	2015-09-03
Low-cost Cmos Structure With Dual Gate Dielectrics And Method Of Forming The Cmos Structure App 20150249088 - Hao; Pinghai ; et al.	2015-09-03
ESD protection circuit with isolated SCR for negative voltage operation Grant 9,099,523 - Salman , et al. August 4, 2	2015-08-04
Deep Collector Vertical Bipolar Transistor With Enhanced Gain App 20150187760 - Hornung; Brian E. ; et al.	2015-07-02
Low Cost Demos Transistor With Improved Chc Immunity App 20150187938 - TANG; Shaoping ; et al.	2015-07-02
Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure Grant 9,064,726 - Hao , et al. June 23, 2	2015-06-23
SRAM cell parameter optimization Grant 9,059,032 - Houston , et al. June 16, 2	2015-06-16
Analog floating-gate capacitor with improved data retention in a silicided integrated circuit Grant 8,975,135 - Liu , et al. March 10, 2	2015-03-10
DEMOS formed with a through gate implant Grant 8,933,510 - Hao , et al. January 13, 2	2015-01-13
Semiconductor interconnect Grant 8,860,147 - Chatterjee , et al. October 14, 2	2014-10-14
Analog Floating-gate Capacitor With Improved Data Retention In A Silicided Integrated Circuit App 20140295631 - LIU; Kaiping ; et al.	2014-10-02
Low-Cost CMOS Structure with Dual Gate Dielectrics and Method of Forming the CMOS Structure App 20140252485 - Hao; Pinghai ; et al.	2014-09-11
Diffusion Resistor With Reduced Voltage Coefficient Of Resistance And Increased Breakdown Voltage Using Cmos Wells App 20140227859 - BENAISSA; Kamel ; et al.	2014-08-14
Analog floating-gate capacitor with improved data retention in a silicided integrated circuit Grant 8,779,550 - Liu , et al. July 15, 2	2014-07-15
Decmos Formed With A Through Gate Implant App 20140183630 - Hao; Pinghai ; et al.	2014-07-03
High Performance Isolated Vertical Bipolar Junction Transistor And Method For Forming In A Cmos Integrated Circuit App 20140183655 - ROBINSON; Derek W. ; et al.	2014-07-03
Pocket counterdoping for gate-edge diode leakage reduction Grant 8,753,944 - Nandakumar , et al. June 17, 2	2014-06-17
Esd Protection Circuit With Isolated Scr For Negative Voltage Operation App 20140124828 - Salman; Akram A. ; et al.	2014-05-08
MOS transistors having reduced leakage well-substrate junctions Grant 8,716,097 - Bordelon, Jr. , et al. May 6, 2	2014-05-06
Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells Grant 8,716,827 - Benaissa , et al. May 6, 2	2014-05-06
I-shaped Gate Electrode For Improved Sub-threshold Mosfet Performance App 20140103440 - Chatterjee; Amitava	2014-04-17
Diffusion Resistor With Reduced Voltage Coefficient Of Resistance And Increased Breakdown Voltage Using Cmos Wells App 20140070361 - Benaissa; Kamel ; et al.	2014-03-13
Drain Extended CMOS with Counter-Doped Drain Extension App 20140061785 - Steinmann; Philipp ; et al.	2014-03-06
Mos Transistors Having Reduced Leakage Well-substrate Junctions App 20140042545 - BORDELON, JR.; Terry James ; et al.	2014-02-13
Pocket Counterdoping For Gate-edge Diode Leakage Reduction App 20140021545 - NANDAKUMAR; MAHALINGAM ; et al.	2014-01-23
Analog Floating-Gate Capacitor with Improved Data Retention in a Silicided Integrated Circuit App 20140001526 - Liu; Kaiping ; et al.	2014-01-02
Drain extended CMOS with counter-doped drain extension Grant 8,592,900 - Steinmann , et al. November 26, 2	2013-11-26
Sram Cell Parameter Optimization App 20120275207 - Houston; Theodore W. ; et al.	2012-11-01
Drain Extended CMOS with Counter-Doped Drain Extension App 20120112275 - Steinmann; Philipp ; et al.	2012-05-10
Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom Grant 8,114,744 - Chatterjee , et al. February 14, 2	2012-02-14
Application of different isolation schemes for logic and embedded memory Grant 8,067,279 - Sadra , et al. November 29, 2	2011-11-29
Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom Grant 8,053,322 - Drobny , et al. November 8, 2	2011-11-08
Method for measuring interface traps in thin gate oxide MOSFETS Grant 7,859,289 - Chatterjee , et al. December 28, 2	2010-12-28
Method For Measuring Interface Traps In Thin Gate Oxide Mosfets App 20100274506 - Chatterjee; Tathagata ; et al.	2010-10-28
Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs Grant 7,795,085 - Yoon , et al. September 14, 2	2010-09-14
Epitaxial Deposition-based Processes For Reducing Gate Dielectric Thinning At Trench Edges And Integrated Circuits Therefrom App 20100163997 - DROBNY; Vladimir F. ; et al.	2010-07-01
Methods For Reducing Gate Dielectric Thinning On Trench Isolation Edges And Integrated Circuits Therefrom App 20100164004 - CHATTERJEE; AMITAVA ; et al.	2010-07-01
Application of different isolation schemes for logic and embedded memory Grant 7,662,688 - Sadra , et al. February 16, 2	2010-02-16
Sidewall spacer pullback scheme Grant 7,638,402 - Nandakumar , et al. December 29, 2	2009-12-29
Application of Different Isolation Schemes for Logic and Embedded Memory App 20090258471 - Sadra; Kayvan ; et al.	2009-10-15
Semiconductor Interconnect App 20090134471 - Chatterjee; Amitava ; et al.	2009-05-28
Method of manufacturing gate sidewalls that avoids recessing Grant 7,514,331 - Yoon , et al. April 7, 2	2009-04-07
Sidewall spacer pullback scheme App 20080160708 - Nandakumar; Mahalingam ; et al.	2008-07-03
Method for measuring interface traps in thin gate oxide MOSFETs App 20080096292 - Chatterjee; Tathagata ; et al.	2008-04-24
Application of Different Isolation Schemes for Logic and Embedded Memory App 20080003772 - Sadra; Kayvan ; et al.	2008-01-03
Application of different isolation schemes for logic and embedded memory Grant 7,314,800 - Sadra , et al. January 1, 2	2008-01-01
Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs App 20070287239 - Yoon; Jong Shik ; et al.	2007-12-13
A Method Of Manufacturing Gate Sidewalls That Avoids Recessing App 20070287258 - Yoon; Jong Shik ; et al.	2007-12-13
Lateral bipolar junction transistor in CMOS flow Grant 7,285,830 - Chatterjee October 23, 2	2007-10-23
Shallow trench isolation method Grant 7,279,397 - Mehrotra , et al. October 9, 2	2007-10-09
Method for manufacturing a semiconductor device using a sidewall spacer etchback Grant 7,229,869 - Yoon , et al. June 12, 2	2007-06-12
Design method and system for optimum performance in integrated circuits that use power management Grant 7,216,310 - Chatterjee , et al. May 8, 2	2007-05-08
Application of different isolation schemes for logic and embedded memory Grant 7,193,277 - Sadra , et al. March 20, 2	2007-03-20
Application of different isolation schemes for logic and embedded memory Grant 7,141,468 - Sadra , et al. November 28, 2	2006-11-28
Isolation region formation that controllably induces stress in active regions App 20060228867 - Mehrotra; Manoj ; et al.	2006-10-12
Multi-layer reducible sidewall process Grant 7,112,497 - Mehrad , et al. September 26, 2	2006-09-26
Method for manufacturing a semiconductor device using a sidewall spacer etchback App 20060205169 - Yoon; Jong Shik ; et al.	2006-09-14
Semiconductor device having optimized shallow junction geometries and method for fabrication thereof Grant 7,098,099 - Hornung , et al. August 29, 2	2006-08-29
Semiconductor device having optimized shallow junction geometries and method for fabrication thereof App 20060189066 - Hornung; Brian E. ; et al.	2006-08-24
Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) Grant 7,045,436 - Chatterjee , et al. May 16, 2	2006-05-16
Method to design for or modulate the CMOS transistor threshold voltage using shallow trench isolation (STI) Grant 7,045,410 - Mehrad , et al. May 16, 2	2006-05-16
Modeling process for integrated circuit film resistors Grant 7,039,888 - Steinmann , et al. May 2, 2	2006-05-02
Application of different isolation schemes for logic and embedded memory App 20060084230 - Sadra; Kayvan ; et al.	2006-04-20
Silicide method for CMOS integrated circuits Grant 7,029,967 - Zhao , et al. April 18, 2	2006-04-18
Method for manufacturing improved sidewall structures for use in semiconductor devices Grant 7,018,888 - Goodlin , et al. March 28, 2	2006-03-28
Forming lateral bipolar junction transistor in CMOS flow App 20060027895 - Chatterjee; Amitava	2006-02-09
Shallow trench isolation method App 20060024909 - Mehrotra; Manoj ; et al.	2006-02-02
Method to design for or modulate the CMOS transistor inverse narrow width effect (INWE) using shallow trench isolation (STI) App 20060024911 - Mehrad; Freidoon ; et al.	2006-02-02
Method for manufacturing improved sidewall structures for use in semiconductor devices App 20060024872 - Goodlin; Brian E. ; et al.	2006-02-02
Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) App 20060024910 - Chatterjee; Amitava ; et al.	2006-02-02
Silicide method for CMOS integrated circuits App 20060019478 - Zhao; Song ; et al.	2006-01-26
Forming lateral bipolar junction transistor in CMOS flow Grant 6,987,039 - Chatterjee January 17, 2	2006-01-17
Multi-layer reducible sidewall process App 20050287751 - Mehrad, Freidoon ; et al.	2005-12-29
Application of different isolation schemes for logic and embedded memory App 20050145949 - Sadra, Kayvan ; et al.	2005-07-07
Design method and system for optimum performance in integrated circuits that use power management App 20050149887 - Chatterjee, Amitava ; et al.	2005-07-07
Modeling process for integrated circuit film resistors App 20050124079 - Steinmann, Philipp ; et al.	2005-06-09
Application of different isolation schemes for logic and embedded memory App 20050087810 - Sadra, Kayvan ; et al.	2005-04-28
Asymmetrical devices for short gate length performance with disposable sidewall Grant 6,873,008 - Houston , et al. March 29, 2	2005-03-29
Compensated-well electrostatic discharge protection devices Grant 6,869,840 - Chatterjee , et al. March 22, 2	2005-03-22
Vertical bipolar transistor formed using CMOS processes Grant 6,858,486 - Chatterjee February 22, 2	2005-02-22
High performance PNP bipolar device fully compatible with CMOS process Grant 6,794,730 - Kim , et al. September 21, 2	2004-09-21
Reduced gate leakage current in thin gate dielectric CMOS integrated circuits Grant 6,791,383 - Chatterjee September 14, 2	2004-09-14
Method to increase substrate potential in MOS transistors used in ESD protection circuits Grant 6,767,810 - Salling , et al. July 27, 2	2004-07-27
Transistor having improved gate structure Grant 6,753,559 - Chatterjee , et al. June 22, 2	2004-06-22
Transistors having selectively doped channel regions Grant 6,730,555 - Kim , et al. May 4, 2	2004-05-04
Compensated-well electrostatic discharge protection devices App 20040080883 - Chatterjee, Amitava ; et al.	2004-04-29
Asymmetrical devices for short gate length performance with disposable sidewall App 20040077138 - Houston, Theodore W. ; et al.	2004-04-22
Reduced gate leakage current in thin gate dielectric CMOS integrated circuits App 20040067600 - Chatterjee, Amitava	2004-04-08
Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask Grant 6,713,334 - Nandakumar , et al. March 30, 2	2004-03-30
Vertical bipolar transistor formed using CMOS processes App 20040046183 - Chatterjee, Amitava	2004-03-11
Method to increase substrate potential in MOS transistors used in ESD protection circuits App 20040021180 - Salling, Craig T. ; et al.	2004-02-05
Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant Grant 6,682,980 - Chidambaram , et al. January 27, 2	2004-01-27
Vertical bipolar transistor formed using CMOS processes Grant 6,649,983 - Chatterjee November 18, 2	2003-11-18
Vertical bipolar transistor formed using CMOS processes Grant 6,646,311 - Chatterjee November 11, 2	2003-11-11
Fabrication Of Abrupt Ultra-shallow Junctions Using Angled Pai And Fluorine Implant App 20030207542 - Chidambaram, P.R. ; et al.	2003-11-06
Compensated-well electrostatic discharge protection structure Grant 6,639,284 - Chatterjee , et al. October 28, 2	2003-10-28
Design method and system for providing transistors with varying active region lengths Grant 6,598,214 - Chatterjee , et al. July 22, 2	2003-07-22
Vertical bipolar transistor formed using CMOS processes App 20030102512 - Chatterjee, Amitava	2003-06-05
Method to increase substrate potential in MOS transistors used in ESD protection circuits App 20030071310 - Salling, Craig T. ; et al.	2003-04-17
Vertical bipolar transistor formed using CMOS processes App 20030067012 - Chatterjee, Amitava	2003-04-10
Forming lateral bipolar junction transistor in CMOS flow App 20030062539 - Chatterjee, Amitava	2003-04-03
Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask App 20030040148 - Nandakumar, Mahalingam ; et al.	2003-02-27
Buried Channel Pmos Transistor In Dual Gate Cmos With Reduced Masking Steps App 20030025165 - Kim, Youngmin ; et al.	2003-02-06
Transistors having selectively doped channel regions App 20020182793 - Kim, Youngmin ; et al.	2002-12-05
Integrated circuit asymmetric transistors Grant 6,482,724 - Chatterjee November 19, 2	2002-11-19
Use of a thin nitride spacer in a split gate embedded analog process Grant 6,479,339 - Nandakumar , et al. November 12, 2	2002-11-12
Asymmetrical devices for short gate length performance with disposable sidewall App 20020145154 - Houston, Theodore W. ; et al.	2002-10-10
Hydrogen treatment for threshold voltage shift of metal gate MOSFET devices Grant 6,420,236 - Hu , et al. July 16, 2	2002-07-16
High performance PNP bipolar device fully compatible with CMOS process App 20020084495 - Kim, Youngmin ; et al.	2002-07-04
Use of sidewall spacer in PNP layout to minimize silicided area of emitter App 20020086489 - Chatterjee, Amitava	2002-07-04
Method To Partially Or Completely Suppress Pocket Implant In Selective Circuit Elements With No Additional Mask In A Cmos Flow Where Separate Masking Steps Are Used For The Drain Extension Implants For The Low Voltage And High Voltage Transistors Grant 6,413,824 - Chatterjee , et al. July 2, 2	2002-07-02
Design method and system for providing transistors with varying active region lengths App 20020083399 - Chatterjee, Amitava ; et al.	2002-06-27
Use of a thin nitride spacer in a split gate embedded analog process App 20020042166 - Nandakumar, Mahalingam ; et al.	2002-04-11
Transistor having improved gate structure App 20010046760 - Chatterjee, Amitava ; et al.	2001-11-29
Integrated circuit insulator and method Grant 6,313,010 - Nag , et al. November 6, 2	2001-11-06
Transistor having an improved sidewall gate structure and method of construction Grant 6,307,230 - Chatterjee , et al. October 23, 2	2001-10-23
Method of making multiple threshold voltage integrated of circuit transistors Grant 6,287,920 - Chatterjee , et al. September 11, 2	2001-09-11
CMP-free disposable gate process Grant 6,232,188 - Murtaza , et al. May 15, 2	2001-05-15
Semiconductor devices with pocket implant and counter doping Grant 6,228,725 - Nandakumar , et al. May 8, 2	2001-05-08
Disposable gate/replacement gate MOSFETs for sub-0.1 micron gate length and ultra-shallow junctions Grant 6,180,978 - Chatterjee , et al. January 30, 2	2001-01-30
Protective liner for isolation trench side walls and method Grant 6,143,625 - Chen , et al. November 7, 2	2000-11-07
Disposable gate/replacement gate MOSFETS for sub-0.1 micron gate length and ultra-shallow junctions Grant 6,127,232 - Chatterjee , et al. October 3, 2	2000-10-03
Semiconductor ESD protection circuit Grant 6,125,021 - Duvvury , et al. September 26, 2	2000-09-26
Method of forming a transistor having an improved sidewall gate structure Grant 6,117,741 - Chatterjee , et al. September 12, 2	2000-09-12
Hydrogen silsesquioxane thin films for low capacitance structures in integrated circuits Grant 6,114,186 - Jeng , et al. September 5, 2	2000-09-05
Lateral SCR structure for ESD protection in trench isolated technologies Grant 6,081,002 - Amerasekera , et al. June 27, 2	2000-06-27
Bistable SCR-like switch for ESD protection of silicon-on-insulator integrated circuits Grant 6,015,992 - Chatterjee , et al. January 18, 2	2000-01-18
Controlled low collector breakdown voltage vertical transistor for ESD protection circuits Grant 5,539,233 - Amerasekera , et al. July 23, 1	1996-07-23
Low voltage triggering semiconductor controlled rectifiers Grant 5,465,189 - Polgreen , et al. November 7, 1	1995-11-07
Method of making a silicon controlled rectifier device for electrostatic discharge protection Grant 5,453,384 - Chatterjee September 26, 1	1995-09-26
Silicon controlled rectifier structure for electrostatic discharge protection Grant 5,225,702 - Chatterjee July 6, 1	1993-07-06
Programmable interconnect or cell using silicided MOS transistors Grant 5,068,696 - Yang , et al. November 26, 1	1991-11-26
Programmable interconnect or cell using silicided MOS transistors Grant 5,019,878 - Yang , et al. May 28, 1	1991-05-28
Efficient ESD input protection scheme Grant 4,896,243 - Chatterjee , et al. January 23, 1	1990-01-23