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Patent applications and USPTO patent grants for Chartered Semiconductor Mfg, Ltd.The latest application filed is for "formation of raised source/drain structures in nfet with embedded sige in pfet".
Patent | Date |
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Double anneal with improved reliability for dual contact etch stop liner scheme App 20070138564 - Lim; Khee Yong ;   et al. | 2007-06-21 |
Formation of raised source/drain structures in NFET with embedded SiGe in PFET App 20070138570 - Chong; Yung Fu ;   et al. | 2007-06-21 |
Embedded stressor structure and process App 20070132038 - Chong; Yung Fu ;   et al. | 2007-06-14 |
Lithography process optimization and system App 20070031744 - Crouse; Michael Matthew ;   et al. | 2007-02-08 |
Method of manufacturing semiconductor local interconnect and contact App 20040155269 - Yelehanka, Pradeep Ramachandramurthy ;   et al. | 2004-08-12 |
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