Chartered Semiconductor Manufacturing, Inc.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Chartered Semiconductor Manufacturing, Inc..The latest application filed is for "method of extreme ultraviolet mask engineering".

Company Profile

0.12.4

Chartered Semiconductor Manufacturing, Inc. - Singapore SG
Chartered Semiconductor Manufacturing Inc. -
Chartered Semiconductor Manufacturing Inc. - Milpitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for performing nickel salicidation Grant 6,890,854 - Lee , et al. May 10, 2	2005-05-10
Method of extreme ultraviolet mask engineering App 20020115000 - Gupta, Subhash ; et al.	2002-08-22
Method for forming variable-K gate dielectric App 20020100947 - Lee, James Yong Meng ; et al.	2002-08-01
Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence App 20020096190 - Roy, Sudipto Ranendra ; et al.	2002-07-25
Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions Grant 6,410,429 - Ho , et al. June 25, 2	2002-06-25
Method for fabricating an air gap shallow trench isolation (STI) structure Grant 6,406,975 - Lim , et al. June 18, 2	2002-06-18
Method to form zirconium oxide and hafnium oxide for high dielectric constant materials App 20020064970 - Chooi, Simon ; et al.	2002-05-30
Method to form a recessed source drain on a trench side wall with a replacement gate technique Grant 6,380,088 - Chan , et al. April 30, 2	2002-04-30
Method to form high performance copper damascene interconnects by de-coupling via and metal line filling Grant 6,380,084 - Lim , et al. April 30, 2	2002-04-30
Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures Grant 6,380,106 - Lim , et al. April 30, 2	2002-04-30
Method of copper transport prevention by a sputtered gettering layer on backside of wafer Grant 6,358,821 - Gupta , et al. March 19, 2	2002-03-19
Method to improve adhesion of organic dielectrics in dual damascene interconnects Grant 6,348,407 - Gupta , et al. February 19, 2	2002-02-19
Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon Grant 6,313,008 - Leung , et al. November 6, 2	2001-11-06
Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials Grant 6,300,177 - Sundaresan , et al. October 9, 2	2001-10-09
Flash memory cell structure with improved channel punch-through characteristics Grant 6,284,603 - Ho Simon , et al. September 4, 2	2001-09-04
Method of forming MOS/CMOS devices with dual or triple gate oxide Grant 6,268,251 - Zhong , et al. July 31, 2	2001-07-31

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.